EP1810GM883 vs EP1810GM883B 比較
詳細並排比較 EP1810GM883 由 Altera 與 EP1810GM883B 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810GM883 | EP1810GM883B |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | Classic EPLD (EP1810 series) | — |
| Device Type | UV-Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 48 | 48 |
| Dedicated Inputs | 12 | 12 |
| User I/O Pins | 48 | — |
| Total Terminals | 68 | — |
| Global Clocks | 4 | — |
| Supply Voltage (Vcc) | 4.5 V to 5.5 V (nominal 5 V) | — |
| Propagation Delay (tpd) | 45 ns (max) | — |
| Maximum Toggle Frequency (fmax) | [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade] | — |
| Process Technology | CMOS, UV-erasable | — |
| 封裝 | 68-Pin Ceramic Pin Grid Array (PGA) | — |
| 工作溫度 | -55C to +125C (MIL-STD-883 Class B) | -55 °C to +125 °C (Military, MIL-STD-883B) |
| Screening | MIL-STD-883 Class B (suffix '883' denotes MIL processing) | — |
| 安裝類型 | Through-Hole (PGA socket) | Through-hole (PGA socket or PCB through-hole) |
| RoHS 狀態 | [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data] | — |
| Lead-Free | [DATA_NEEDED: military 883B screened parts commonly use SnPb finish] | — |
| Device Family | — | EP1810 (Classic EPLD) |
| User Flip-Flops | — | Up to 64 |
| Total Inputs | — | 60 |
| I/O Pins | — | 48 (bidirectional, tri-state) |
| Propagation Delay (tPD) | — | 50 ns max |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V |
| Technology | — | CMOS, UV-erasable |
| Package Type | — | Ceramic Pin Grid Array (PGA), 84 pins |
| Package Designator | — | GM (ceramic PGA) |
| Processing Level | — | MIL-STD-883B (Class B) |
| Programming Method | — | UV-erasable / Altera programming hardware |
| Lead-Free / RoHS | — | [DATA_NEEDED: lead-free status] |
| Logic Family | — | TTL-compatible I/O |