EP1810GM883 vs EP1810JM-45 比較
詳細並排比較 EP1810GM883 由 Altera 與 EP1810JM-45 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810GM883 | EP1810JM-45 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Classic EPLD (EP1810 series) | — |
| Device Type | UV-Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 48 | 48 |
| Dedicated Inputs | 12 | — |
| User I/O Pins | 48 | — |
| Total Terminals | 68 | — |
| Global Clocks | 4 | — |
| Supply Voltage (Vcc) | 4.5 V to 5.5 V (nominal 5 V) | — |
| Propagation Delay (tpd) | 45 ns (max) | 45 ns (max, -45 speed grade) |
| Maximum Toggle Frequency (fmax) | [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade] | — |
| Process Technology | CMOS, UV-erasable | — |
| 封裝 | 68-Pin Ceramic Pin Grid Array (PGA) | — |
| 工作溫度 | -55C to +125C (MIL-STD-883 Class B) | -55 C to +125 C (military grade) |
| Screening | MIL-STD-883 Class B (suffix '883' denotes MIL processing) | — |
| 安裝類型 | Through-Hole (PGA socket) | Surface Mount (J-lead) |
| RoHS 狀態 | [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data] | [DATA_NEEDED: RoHS status - legacy mil-spec part] |
| Lead-Free | [DATA_NEEDED: military 883B screened parts commonly use SnPb finish] | — |
| Device Family | — | Classic EPLD (EP1810 series) |
| Usable Gates | — | ~900 gates |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V |
| Technology | — | CMOS, UV-EPROM configuration |
| Package Type | — | JLCC-68 (ceramic J-leaded chip carrier) |
| Package Code | — | JM (windowed ceramic, UV-erasable) |
| 腳位數 | — | 68 |
| I/O Compatibility | — | CMOS / TTL |
| Configuration Method | — | JEDEC fuse map, EPROM programmer |
| Programming Technology | — | UV-erasable EPROM (non-volatile, instant-on) |
| Logic Type | — | EPLD / PLD (programmable logic device) |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |