EP1810GM883B vs EP1810GC-35 比較
詳細並排比較 EP1810GM883B 由 Altera 與 EP1810GC-35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810GM883B | EP1810GC-35 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | 最後購買 |
| Device Family | EP1810 (Classic EPLD) | — |
| Macrocells | 48 | 16 |
| User Flip-Flops | Up to 64 | — |
| Total Inputs | 60 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 (bidirectional, tri-state) | — |
| Propagation Delay (tPD) | 50 ns max | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Technology | CMOS, UV-erasable | CMOS, UV-erasable EPROM cells |
| 工作溫度 | -55 °C to +125 °C (Military, MIL-STD-883B) | [DATA_NEEDED: operating temperature range] |
| Package Type | Ceramic Pin Grid Array (PGA), 84 pins | — |
| Package Designator | GM (ceramic PGA) | — |
| Processing Level | MIL-STD-883B (Class B) | — |
| Programming Method | UV-erasable / Altera programming hardware | UV erasure + EPROM programming |
| 安裝類型 | Through-hole (PGA socket or PCB through-hole) | Through Hole |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free status] | — |
| Logic Family | TTL-compatible I/O | Altera Classic EPLD |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| 封裝 | — | CPGA-68 (Ceramic Pin Grid Array, 68-pin) |
| 腳位數 | — | 68 |
| Propagation Delay (tpd max) | — | 40 ns |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| I/O Standard | — | TTL-compatible |
| 供應電壓 | — | [DATA_NEEDED: VCC range] |
| RoHS 狀態 | — | Not applicable (legacy ceramic package) |
| Lead-Free Status | — | Not applicable |
| Manufacturer (current source) | — | Rochester Electronics (authorized Altera EPLD partner) |
| Original Manufacturer | — | Altera Corporation (now Intel FPGA) |