EP1810JC-45 vs EP1810GC-35AB 比較
詳細並排比較 EP1810JC-45 由 Altera 與 EP1810GC-35AB 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810JC-45 | EP1810GC-35AB |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP1810 (Classic EPLD Family) | — |
| Macrocells | 48 | — |
| Equivalent Gates | 2100 gates | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 | — |
| Total User I/O | 60 | — |
| Propagation Delay (tpd) | 45 ns | — |
| 最大時脈頻率 | 33.3 MHz | — |
| Technology | CMOS, UV-erasable | CMOS EPROM |
| Maximum Supply Voltage | 5.25 V | — |
| 封裝 | PLCC-68 (QCCJ, J-Lead, windowed ceramic) | — |
| 腳位數 | 68 | — |
| Package Code | QCCJ | — |
| Temperature Grade | Commercial | — |
| 安裝類型 | Surface Mount | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance not stated in verified data] | unknown |
| Product Family | — | Classic EPLD |
| Number of Macrocells | — | 48 |
| Number of Usable Gates | — | 1200 |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| Number of I/O Pins | — | 48 |
| Dedicated Input Pins | — | 12 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Toggle Frequency | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Package Type | — | Pin Grid Array (PGA), ceramic |
| 工作溫度 | — | [DATA_NEEDED: operating temperature range] |
| Programming Method | — | UV-erasable EPROM, in-system via JTAG-like interface |