EP1810JI-35 vs EP1810GM883B 比較
詳細並排比較 EP1810JI-35 由 Intel 與 EP1810GM883B 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810JI-35 | EP1810GM883B |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Device Family | Classic EPLD | EP1810 (Classic EPLD) |
| Macrocells | 48 | 48 |
| Logic Array Blocks | 8 LABs of 16 macrocells | — |
| Dedicated Inputs | 48 | 12 |
| Pin-to-Pin Propagation Delay (tPD) | 35 ns | — |
| Speed Grade | -35 | — |
| 封裝 | 28-pin JLCC (J-leaded ceramic, windowed) | — |
| Process Technology | CMOS EPROM (UV-erasable) | — |
| 工作溫度 | -40C to +85C (Industrial) | -55 °C to +125 °C (Military, MIL-STD-883B) |
| 供應電壓 | 5 V (typical classic EPLD) | — |
| Programmability | UV-erase, windowed for lab reprogram | — |
| 安裝類型 | Through-Hole (J-lead) | Through-hole (PGA socket or PCB through-hole) |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] | — |
| MSL 等級 | [DATA_NEEDED: MSL rating] | — |
| Programming Interface | JEDEC fuse file via legacy programmer | — |
| User Flip-Flops | — | Up to 64 |
| Total Inputs | — | 60 |
| I/O Pins | — | 48 (bidirectional, tri-state) |
| Propagation Delay (tPD) | — | 50 ns max |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V |
| Technology | — | CMOS, UV-erasable |
| Package Type | — | Ceramic Pin Grid Array (PGA), 84 pins |
| Package Designator | — | GM (ceramic PGA) |
| Processing Level | — | MIL-STD-883B (Class B) |
| Programming Method | — | UV-erasable / Altera programming hardware |
| Lead-Free / RoHS | — | [DATA_NEEDED: lead-free status] |
| Logic Family | — | TTL-compatible I/O |