EP1810JM-45 vs EP1810GI-45 比較
詳細並排比較 EP1810JM-45 由 Altera 與 EP1810GI-45 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810JM-45 | EP1810GI-45 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | Classic EPLD (EP1810 series) | — |
| Macrocells | 48 | 24 |
| Usable Gates | ~900 gates | — |
| Propagation Delay (tpd) | 45 ns (max, -45 speed grade) | 45 ns |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Technology | CMOS, UV-EPROM configuration | CMOS |
| Package Type | JLCC-68 (ceramic J-leaded chip carrier) | Ceramic Pin Grid Array with UV window |
| Package Code | JM (windowed ceramic, UV-erasable) | — |
| 腳位數 | 68 | 68 |
| 工作溫度 | -55 C to +125 C (military grade) | [DATA_NEEDED: operating temperature range] |
| I/O Compatibility | CMOS / TTL | — |
| Configuration Method | JEDEC fuse map, EPROM programmer | — |
| Programming Technology | UV-erasable EPROM (non-volatile, instant-on) | — |
| 安裝類型 | Surface Mount (J-lead) | Through-Hole |
| Logic Type | EPLD / PLD (programmable logic device) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status - legacy mil-spec part] | Non-compliant (ceramic PGA) |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| Device Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Family | — | Altera Classic EPLD |
| Flip-Flops | — | 48 |
| Speed Grade | — | -45 |
| Programmable | — | Yes (UV-erasable, electrically programmable) |
| Lead-Free | — | No |
| 供應電壓 | — | [DATA_NEEDED: VCC range] |