EP1810LC-20 vs EP1810LC-30 比較
詳細並排比較 EP1810LC-20 由 Intel 與 EP1810LC-30 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810LC-20 | EP1810LC-30 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Classic EPLD | Altera Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Usable Gates | 900 | — |
| Macrocells | 48 | 48 |
| Maximum Operating Frequency | 50 MHz | — |
| Propagation Delay (tPD) | 20 ns | — |
| 供應電壓 | 5 V (4.75 V to 5.25 V) | 5 V (typical) |
| Technology | CMOS EPROM | CMOS, low-power (LC) |
| Programmability | UV-Erasable / OTP | — |
| Dedicated Inputs | 12 | — |
| 封裝 | 68-pin PLCC | JLCC-68 (68-pin J-Lead ceramic chip carrier) |
| Package Suffix | LC (PLCC, windowed for UV erase on L variant) | — |
| Speed Grade | 20 ns (commercial) | — |
| 工作溫度 | 0C to +70C (commercial) | [DATA_NEEDED: temperature grade] |
| 安裝類型 | Surface Mount | — |
| RoHS 狀態 | [DATA_NEEDED: rohs status] | unknown (legacy ceramic package) |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Flip-Flops | — | 48 (one per macrocell) |
| Speed Grade (tPD) | — | 30 ns |
| Programming | — | Device programmer or JTAG |
| Standby Current | — | [DATA_NEEDED: ICC standby] |
| 腳位數 | — | 68 |
| Number of I/O Pins | — | [DATA_NEEDED: I/O count] |
| Logic Blocks | — | 48 macrocells |