EP1810LC-20 vs EP1810LC-45 比較
詳細並排比較 EP1810LC-20 由 Intel 與 EP1810LC-45 由 Rochester Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP1810LC-45 - 900-Gate Classic EPLD, 48 Macro Cells, PLCC-68 | Intel
EP1810LC-45 Obsolete規格比較
| 參數 | EP1810LC-20 | EP1810LC-45 |
|---|---|---|
| 品牌 | Intel | Rochester Electronics |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Classic EPLD | Altera Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | 900 | 900 |
| Macrocells | 48 | — |
| Maximum Operating Frequency | 50 MHz | 22.2 MHz |
| Propagation Delay (tPD) | 20 ns | — |
| 供應電壓 | 5 V (4.75 V to 5.25 V) | — |
| Technology | CMOS EPROM | — |
| Programmability | UV-Erasable / OTP | — |
| Dedicated Inputs | 12 | — |
| 封裝 | 68-pin PLCC | 68-pin PLCC (J-lead) |
| Package Suffix | LC (PLCC, windowed for UV erase on L variant) | — |
| Speed Grade | 20 ns (commercial) | — |
| 工作溫度 | 0C to +70C (commercial) | 0 °C to +70 °C (commercial) |
| 安裝類型 | Surface Mount | Surface Mount (PLCC socket compatible) |
| RoHS 狀態 | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status of Rochester-sourced part] |
| Macro Cells | — | 48 |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| Logic Array Blocks | — | 4 |
| Propagation Delay (tpd) | — | 45 ns |
| Supply Voltage (Vcc) | — | 5 V (±5%) |
| Process Technology | — | 5 V CMOS EPROM |
| Lead-Free | — | [DATA_NEEDED: lead-free finish] |