EP1810LC-20T vs EP1810LC-20 比較
詳細並排比較 EP1810LC-20T 由 Intel 與 EP1810LC-20 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810LC-20T | EP1810LC-20 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Classic EPLD |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 900 gates | 900 |
| Macrocells | 48 | 48 |
| Logic Array Blocks (LABs) | 4 x 12 macrocells | — |
| Maximum Toggle Frequency | 50 MHz | — |
| Pin-to-Pin Logic Delay (tPD) | 20 ns | — |
| Supply Voltage (VCC) | 5 V | — |
| Package Type | PLCC-68 (J-lead) | — |
| 安裝類型 | Surface Mount (socket-compatible) | Surface Mount |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Programming Interface | JTAG (IEEE 1149.1) and Altera Master/Slave serial | — |
| 工作溫度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Shipping Format | Tape & Reel ("T" suffix) | — |
| RoHS 狀態 | Non-compliant (legacy 5V PLCC) | [DATA_NEEDED: rohs status] |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Maximum Operating Frequency | — | 50 MHz |
| Propagation Delay (tPD) | — | 20 ns |
| 供應電壓 | — | 5 V (4.75 V to 5.25 V) |
| Technology | — | CMOS EPROM |
| Programmability | — | UV-Erasable / OTP |
| Dedicated Inputs | — | 12 |
| 封裝 | — | 68-pin PLCC |
| Package Suffix | — | LC (PLCC, windowed for UV erase on L variant) |
| Speed Grade | — | 20 ns (commercial) |