EP1810LC-30 vs EP1810GC-35 比較
詳細並排比較 EP1810LC-30 由 Altera 與 EP1810GC-35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810LC-30 | EP1810GC-35 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | — |
| Macrocells | 48 | 16 |
| Flip-Flops | 48 (one per macrocell) | — |
| Speed Grade (tPD) | 30 ns | — |
| 供應電壓 | 5 V (typical) | [DATA_NEEDED: VCC range] |
| Technology | CMOS, low-power (LC) | CMOS, UV-erasable EPROM cells |
| 封裝 | JLCC-68 (68-pin J-Lead ceramic chip carrier) | CPGA-68 (Ceramic Pin Grid Array, 68-pin) |
| Programming | Device programmer or JTAG | — |
| 工作溫度 | [DATA_NEEDED: temperature grade] | [DATA_NEEDED: operating temperature range] |
| Standby Current | [DATA_NEEDED: ICC standby] | — |
| 腳位數 | 68 | 68 |
| Number of I/O Pins | [DATA_NEEDED: I/O count] | — |
| Logic Blocks | 48 macrocells | — |
| RoHS 狀態 | unknown (legacy ceramic package) | Not applicable (legacy ceramic package) |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Family | — | Altera Classic EPLD |
| Propagation Delay (tpd max) | — | 40 ns |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| I/O Standard | — | TTL-compatible |
| Programming Method | — | UV erasure + EPROM programming |
| 安裝類型 | — | Through Hole |
| Lead-Free Status | — | Not applicable |
| Manufacturer (current source) | — | Rochester Electronics (authorized Altera EPLD partner) |
| Original Manufacturer | — | Altera Corporation (now Intel FPGA) |