EP1810LI-25 vs EP1810LC-45 比較
詳細並排比較 EP1810LI-25 由 Altera 與 EP1810LC-45 由 Rochester Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP1810LC-45 - 900-Gate Classic EPLD, 48 Macro Cells, PLCC-68 | Intel
EP1810LC-45 Obsolete規格比較
| 參數 | EP1810LI-25 | EP1810LC-45 |
|---|---|---|
| 品牌 | Altera | Rochester Electronics |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device), UV-erasable / OTP | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 48 | — |
| Usable Gates | 900 | 900 |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Counter Frequency | 40 MHz | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) | — |
| I/O Pins | 48 | — |
| Dedicated Inputs | 12 | — |
| Global Clock Inputs | 4 | — |
| Interconnect | Programmable global and local buses | — |
| 封裝 | 68-pin PLCC (J68, J-Lead) | 68-pin PLCC (J-lead) |
| JESD-30 Package Code | S-PQCC-J68 | — |
| Process Technology | CMOS | 5 V CMOS EPROM |
| Operating Temperature (Industrial 'I' suffix) | -40 C to +85 C | — |
| Programming Mode | EPROM/UV-erasable (windowed) and OTP | — |
| Development Tool | Altera MAX+PLUS II | — |
| RoHS 狀態 | unknown | [DATA_NEEDED: RoHS status of Rochester-sourced part] |
| Lead-Free Status | unknown | — |
| Macro Cells | — | 48 |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| Logic Array Blocks | — | 4 |
| Propagation Delay (tpd) | — | 45 ns |
| Maximum Operating Frequency | — | 22.2 MHz |
| Supply Voltage (Vcc) | — | 5 V (±5%) |
| 工作溫度 | — | 0 °C to +70 °C (commercial) |
| 安裝類型 | — | Surface Mount (PLCC socket compatible) |
| Lead-Free | — | [DATA_NEEDED: lead-free finish] |