EP1810LI-35 vs EP1830-20CFN 比較
詳細並排比較 EP1810LI-35 由 Altera 與 EP1830-20CFN 由 Texas Instruments. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810LI-35 | EP1830-20CFN |
|---|---|---|
| 品牌 | Altera | Texas Instruments |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Manufacturer | Rochester Electronics, LLC (original Altera design) | — |
| Part Family | Altera Classic EPLD | — |
| Device Type | Erasable Programmable Logic Device (EPLD) | Erasable Programmable Logic Device (EPLD) |
| Macrocells | 48 | — |
| Propagation Delay (tPD) | 35 ns | 22 ns |
| Speed Grade | 35 (slowest in EP1810L family) | -20 |
| 封裝 | 68-pin PLCC (J-Lead, plastic) | PLCC-68 (QCCJ, J-lead) |
| Pin/Package Code | PLCC-68 / PQCC68 | — |
| Technology | CMOS, UV-erasable EPROM configuration cell | CMOS EPROM |
| 供應電壓 | 5 V (TTL-compatible I/O) | — |
| 工作溫度 | -40 C to +85 C (industrial, 'I' suffix) | — |
| 安裝類型 | Surface Mount (PLCC socket compatible) | — |
| JTAG Boundary Scan | IEEE 1149.1 compliant | — |
| Logic Elements | Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL 等級 | [DATA_NEEDED: MSL rating] | — |
| Macrocell Count | — | 48 |
| Maximum Supply Voltage | — | 5.25 V |
| I/O Pins | — | 48 |
| Dedicated Inputs | — | 12 |
| Terminal Pitch | — | 1.27 mm |
| Terminal Form | — | J-Bend |
| Package Code | — | QCCJ |
| Package Shape | — | Square |
| Operating Temperature Grade | — | Commercial (0C to 70C) |
| Typical Operating Current | — | 20 mA at 1 MHz |
| Maximum Counter Frequency | — | 50 MHz (4 x 12-bit counters) |
| Configuration Memory | — | Non-volatile EPROM (UV-erasable) |