EP1K30TI144-2 vs EP1K30TI144-2NGA 比較

詳細並排比較 EP1K30TI144-2 由 Intel 與 EP1K30TI144-2NGA 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP1K30TI144-2 EP1K30TI144-2NGA
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family ACEX-1K —
Series EP1K30 ACEX 1K
Logic Elements / Cells 1728 1728
Total RAM Bits 24576 24576
Number of Logic Array Blocks (LABs) 216 216
Equivalent Gates 30,000 —
User I/O Count 102 —
Number of I/O Banks 4 —
Supply Voltage - Core 2.5 V (2.375 V min, 2.625 V max) —
Supply Voltage - I/O 2.5 V / 3.3 V / 5.0 V (multiVolt) —
Maximum Internal Frequency 200 MHz —
Process Technology 0.22 µm CMOS, SRAM-based 0.18 um SRAM CMOS
Embedded Memory Type Dual-port EAB (Embedded Array Block) —
封裝 144-LQFP (TQFP), 22 mm × 22 mm, 0.5 mm pitch —
工作溫度 -40 °C to +85 °C (Industrial, "I" suffix) -40C to +85C (Industrial)
Speed Grade -2 (mid-tier) -2 (faster than -3)
Configuration Method SRAM, requires external configuration PROM (EPC) —
Programming Interface JTAG (IEEE 1149.1) / IEEE 1532 ISP —
安裝類型 Surface Mount Surface Mount
RoHS 狀態 [DATA_NEEDED: RoHS compliance - legacy part] —
Number of I/O — 102
Number of Gates (typical) — 119000
Core Voltage (VCCINT) — 2.5 V
I/O Supply Voltage (VCCIO) — 3.3 V
封裝 / 外殼 — 144-LFQFP / 144-TQFP (20x20 mm)
Programmable Logic Type — In-system programmable SRAM FPGA
Lead Free / RoHS Status — Lead free / RoHS compliant per suffix code
Design Software — Quartus II, MAX+PLUS II
JTAG Support — Yes (IEEE 1149.1 boundary scan)
Configuration — SRAM-based, requires configuration device at power-up

資料表與資源

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