EP1K50TC144-1 vs EP1K30TC144-1N 比較

詳細並排比較 EP1K50TC144-1 由 Altera 與 EP1K30TC144-1N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP1K50TC144-1 EP1K30TC144-1N
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND Obsolete
Family ACEX-1K —
Logic Elements / Cells 2,880 —
System Gates 50,000 —
Embedded Memory (Bits) 40,960 —
Logic Array Blocks (LABs) 360 —
User I/O Pins 102 —
Core Voltage 2.5 V 2.5 V
I/O Voltage 2.5 V (5-V tolerant I/O) 3.3 V (LVCMOS/LVTTL); 2.5 V tolerant
Maximum Internal Frequency 250 MHz —
Process Technology CMOS 0.18 µm SRAM
Embedded Array Blocks (EABs) Dual-port, configurable as RAM/ROM —
封裝 144-pin LQFP (TQFP) —
安裝類型 Surface Mount (Gull-Wing Leads) Surface Mount
Operating Temperature Grade Commercial —
Programming Interface JTAG (IEEE 1149.1) + serial configuration —
Development Tools MAX+PLUS II, Quartus —
Lead-Free / RoHS [DATA_NEEDED: Lead-free / RoHS status] —
MSL 等級 [DATA_NEEDED: MSL moisture sensitivity level] [DATA_NEEDED: MSL moisture sensitivity level]
Series — ACEX-1K
Number of Logic Elements (LEs) — 1,728
Typical Gates — 30,000
Number of Logic Array Blocks (LABs) — 216
Embedded Memory (EAB) — 24,576 bits (6 EABs)
Number of User I/O — 102
Number of I/O Banks — 4
Package Type — 144-LQFP (TQFP)
工作溫度 — [DATA_NEEDED: operating temperature range]
Configuration — SRAM-based, JTAG (IEEE 1149.1) + serial/parallel passive
PLLs — 6 (per device family)
RoHS 狀態 — [DATA_NEEDED: RoHS compliance status]
Lead-Free — [DATA_NEEDED: lead-free status]

資料表與資源

瀏覽所有產品 建立 BOM 索取報價