EP1S20F484C6N vs EP1S10F484C5N 比較

詳細並排比較 EP1S20F484C6N 由 Intel 與 EP1S10F484C5N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP1S20F484C6N EP1S10F484C5N
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND Obsolete
Family Stratix Stratix (original)
Logic Elements 18,460 —
Embedded Memory 1,669,248 bits —
DSP Blocks [DATA_NEEDED: DSP block count] —
User I/O Pins 361 —
封裝 484-Ball FCBGA (23 x 23 mm, 1.0 mm pitch) 484-ball FCBGA (F484), 23 x 23 mm, 1.0 mm pitch
Process Technology 130 nm CMOS 0.13 µm CMOS
Core Supply Voltage 1.5 V —
I/O Supply Voltage [DATA_NEEDED: I/O voltage - check datasheet] —
工作溫度 0 C to 85 C (Commercial) —
Speed Grade 6 —
Maximum Internal Clock 450.05 MHz —
Configuration Interface JTAG (IEEE 1149.1), Serial/Parallel (AS/PS) - EPC device compatible —
安裝類型 Surface Mount Surface Mount
RoHS 狀態 [DATA_NEEDED: confirm via Intel product page] —
Lead-Free [DATA_NEEDED: confirm] —
Series — Stratix
Logic Elements (LEs) — 10,570
Logic Array Blocks (LABs) — 1,057
Embedded Memory Bits — 920,448
TriMatrix Memory Blocks — 14
Embedded DSP Blocks — 6 (≈48 9-bit multipliers)
PLLs — 4
Global Clock Networks — 12
Maximum User I/O — 335
User I/O Standard Support — LVDS, LVPECL, PCI-X, RapidIO, DDR
Core Voltage (VCCINT) — 1.5 V
Maximum Internal Frequency — 500 MHz (per Stratix datasheet)
Operating Temperature (TJ) — 0 °C to 85 °C (Commercial)
Configuration Method — JTAG / Passive Serial / Active Serial
Device Status — Obsolete - last time buy completed
Design Toolchain — Quartus II (≤ v13.0)

資料表與資源

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