Intel

EP1S40F1020C5DM - Stratix FPGA 41250LE 1020-BGA | Intel

Name: EP1S40F1020C5DM - Stratix FPGA 41250LE 1020-BGA | Intel
Brand: Intel
SKU: EP1S40F1020C5DM

MPN： EP1S40F1020C5DM ✗ 停產

1.5 V Vdss 1020-ball FineLine BGA (33 mm x 33 mm, 1.0 mm pitch) Package 16 Speed 3,423 Kbits TriMatrix Memory

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MOQ： 1 |

查看資料表 (PDF) 查看替代品

數量

EP1S40F1020C5DM 概覽

The Intel (formerly Altera) EP1S40F1020C5DM is a member of the Stratix FPGA family, featuring 41,250 logic elements, 773 user I/O pins, and 3.4 Mbits of embedded RAM, packaged in a 1020-ball FineLine BGA. Built on a 0.13 µm CMOS process, this device integrates up to 12 embedded DSP blocks for high-performance signal processing, plus 6 phase-locked loops (PLLs) for flexible clock management. The EP1S40F1020C5DM operates across commercial temperature grades and supports LVDS, LVTTL, LVCMOS, SSTL, and HSTL I/O standards with up to 45 high-speed LVDS channels.

An FPGA (Field-Programmable Gate Array) is a semiconductor device built around an array of configurable logic blocks (CLBs), programmable interconnect, and I/O cells that engineers can reconfigure post-manufacture to implement custom digital logic. Stratix FPGAs occupy the high-performance tier of programmable logic, sitting between CPLDs (smaller, simpler) and ASICs (custom-fabricated, non-programmable). The EP1S40F1020C5DM's combination of logic density, embedded memory, DSP blocks, and high-speed transceivers makes it suitable for systems that previously required a custom ASIC.

Key features include 41,250 logic elements, 3,423 Kbits of TriMatrix embedded memory (true dual-port, simple dual-port, and single-port modes), 12 DSP blocks delivering up to 28.8 GMACS at 200 MHz, six PLLs with eight output clocks each, and 16 clock networks across the device. The configuration scheme supports passive serial (PS), passive parallel synchronous (PPS), passive parallel asynchronous (PPA), and JTAG modes via dedicated configuration pins. The 1020-ball FineLine BGA supports high I/O count while enabling dense PCB routing.

The architecture uses 1.5 V core VCCINT with separate VCCIO banks supporting 1.5 V, 1.8 V, 2.5 V, and 3.3 V mixed-voltage interfacing. Distributed and row/column interconnect resources deliver fast, predictable timing closure for high-speed datapaths, and the embedded memory can be configured as FIFO, ROM, or RAM with byte-enable parity. The DSP blocks implement 9-bit × 9-bit, 18-bit × 18-bit, and 36-bit × 36-bit multipliers with adders and accumulators.

Typical applications include high-performance digital signal processing for telecom base stations, HD video broadcast equipment, military radar front-end processing, high-speed serial protocol bridging (PCI Express, RapidIO, Gigabit Ethernet), and ASIC prototyping where designers map production logic to a Stratix device before committing to silicon.

When designing with this device, allocate separate PCB layers for VCCINT, VCCIO, and GND planes, and place all decoupling capacitors within 5 mm of each BGA ball. Use the Quartus II design software for synthesis, place-and-route, and timing closure; legacy Altera legacy designs may require a Quartus II service pack migration.

This page synthesizes distributor availability, drop-in alternatives from the Stratix family, and practical design notes that complement the manufacturer datasheet.

直接替換替代品，適用於 EP1S40F1020C5DM — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。

此系列的變體

與下列產品可直接替換的同系列型號： EP1S40F1020C5DM （相同外形與佔位） — 差異在於 Package, DSP Blocks, Mounting Type, Process Technology, Embedded Memory.

EP1S40F1020C5

Intel

Package: 1020-ball FC-FBGA (33 mm x 33 mm)

DSP Blocks: Yes (dedicated hardware multipliers)

Process Technology: 130 nm

比較對象 EP1S40F1020C5DM →

EP1S40F1020C5AA

Intel

Package: 1020-ball FC-FBGA

DSP Blocks: 14

Process Technology: 130 nm CMOS

比較對象 EP1S40F1020C5DM →

EP1S40F1020C5GA

Intel

Package: 1020-BBGA (FineLine BGA)

DSP Blocks: Embedded multiplier blocks (count per Stratix datasheet family)

Mounting Type: Surface Mount

比較對象 EP1S40F1020C5DM →

EP1S40F1020C6

Altera

Package: 1020-BBGA, FC-FBGA, 33 x 33 mm, 1.0 mm pitch

Mounting Type: Surface Mount (FCBGA)

比較對象 EP1S40F1020C5DM →

EP1S40F1020C5

✅ 直接替換

Intel

📦 1020-ball FineLine BGA

Stratix · Stratix I · 41,250 · 4,125 · 773 · 3.4 Mbits (TriMatrix) · Yes (dedicated hardware multipliers) · 130 nm

聯絡詢價

查看資料表 →

EP1S40F1020C5AA

✅ 直接替換

Intel

📦 1020-ball FineLine BGA

Stratix · 41,250 · 3,423 Kbit · 773 · 14 · 4 · 130 nm CMOS · 1.5 V

聯絡詢價

查看資料表 →

ℹ️ 2 跨封裝零件已隱藏 — 不同封裝需重新加工 PCB，並非真正的直接替換品。聯絡我們如果您需要跨封裝建議。

EP1S40F1020C5DM 最大額定值與電氣特性

Product Type	FPGA - Field Programmable Gate Array
Series	Stratix
Logic Elements	41,250
Embedded Memory	3,423 Kbits TriMatrix
User I/O Count	773
Number of LABs/CLBs	4125
DSP Blocks	12 (up to 28.8 GMACS at 200 MHz)
Number of PLLs	6 (8 outputs each)
Number of Clock Networks	16
封裝	1020-ball FineLine BGA (33 mm x 33 mm, 1.0 mm pitch)
Core Voltage VCCINT	1.5 V
I/O Voltage VCCIO	1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-dependent)
Process Technology	0.13 µm CMOS
工作溫度	0C to +85C (commercial)
Configuration Modes	PS, PPS, PPA, JTAG
安裝類型	Surface Mount (BGA)

EP1S40F1020C5DM 1020-ball fineline bga (33 mm x 33 mm, 1.0 mm pitch) 腳位配置指南

EP1S40F1020C5DM（1020-ball fineline bga (33 mm x 33 mm, 1.0 mm pitch) 封裝）的腳位配置。此數位 IC 包含 GPIO、通訊介面（UART、SPI、I2C）與電源腳位。替代腳位功能與配置選項請參閱製造商資料表。對嵌入式系統設計與 PCB 佈局至關重要。

EP1S40F1020C5DM 的 1020-ball fineline bga (33 mm x 33 mm, 1.0 mm pitch) 封裝腳位圖

無詳細腳位定義資料： EP1S40F1020C5DM.

請參閱資料表以查看完整腳位配置。

典型應用

EP1S40F1020C5DM 適用於 8 應用s: Telecom Base Station Channel Card, HD Video Broadcast Encoder, Military Radar Front-End Processing, ASIC Prototyping Platform, High-Speed Serial Protocol Bridge, Industrial Machine Vision Inspection, Medical Imaging Reconstruction, Software-Defined Radio Baseband.

🌐

Telecom Base Station Channel Card

The EP1S40F1020C5DM fits telecom base-station channel cards because its 41,250 logic elements and 12 DSP blocks deliver up to 28.8 GMACS at 200 MHz, enough to implement digital up/down-conversion (DUC/DDC), crest-factor reduction (CFR), and digital pre-distortion (DPD) for multi-carrier power amplifiers. The 773 user I/O pins expose enough LVDS and LVCMOS pairs for parallel ADC/DAC interfacing, and the six PLLs with eight output clocks each simplify multi-clock domain synthesis for CPRI/OBSAI fronthaul links. Use the Altera CPRI MegaCore or build a custom PHY in the FPGA fabric.

推薦

📺

HD Video Broadcast Encoder

EP1S40F1020C5DM is widely deployed in HD video broadcast encoders because its TriMatrix embedded memory (3,423 Kbits) provides enough on-chip buffering for HD-SDI or 3G-SDI line buffers, while the DSP blocks accelerate motion-estimation and DCT transforms required for MPEG-2/H.264 encoding. The 1020-ball BGA supports enough LVDS pairs to drive multiple SDI outputs simultaneously, and the high I/O count allows parallel connection to external DDR2 SDRAM for frame store. Quartus II 9.1 includes Altera Video and Image Processing (VIP) MegaCores for production use.

推薦

EP1S25F672C7 · Intel EP1S20F672C7 · Intel

✈️

Military Radar Front-End Processing

Military phased-array radar and signal-intelligence systems use EP1S40F1020C5DM to perform digital beamforming, pulse compression, and MTI/MTD filtering on raw ADC data streams. The 12 DSP blocks handle complex 18-bit x 18-bit FIR filtering at high sample rates, and the 773 user I/O pins accept multi-channel LVDS data from synchronized ADC banks. Industrial or military temperature screening (DM / AA suffix) extends operation into harsh environments. Designers use Altera's FFT MegaCore for spectral analysis.

推薦

EP1S40F1020C5AA · Intel EP1S30F1020I6 · Intel

🖥️

ASIC Prototyping Platform

Engineers map production ASIC RTL to the EP1S40F1020C5DM for pre-silicon validation, using its 41,250 LE to absorb mid-sized SoC designs and the 3,423 Kbits of TriMatrix memory to mimic on-chip SRAM blocks. Quartus II's incremental compile flow supports multi-engineer team-based design partitioning, and the JTAG configuration mode enables rapid in-system reprogramming during bring-up. Multiple FPGAs can be wired together via LVDS chip-to-chip links to prototype larger ASICs that exceed single-chip logic capacity.

推薦

EP1S60F1020C5 · Intel EP1S40F1020C5 · Intel

🔧

High-Speed Serial Protocol Bridge

EP1S40F1020C5DM implements protocol-bridge applications such as PCI Express Gen1 to Serial RapidIO, or Gigabit Ethernet to Fibre Channel, because its logic density is sufficient for full protocol stacks including MAC, PCS, and PMA-equivalent soft logic. The 6 PLLs provide the multiple clock domains required for independent transmit/receive paths, and the LVDS I/O capability supports multiple high-speed serial lanes aggregated via SERDES soft-IP. Designers pair the FPGA with external PHY devices for physical-layer signaling.

推薦

EP1S25F780I6N · Intel EP1S20F672C7 · Intel

🏭

Industrial Machine Vision Inspection

Machine-vision systems use EP1S40F1020C5DM to ingest Camera Link or CoaXPress image data, perform real-time preprocessing (white balance, gamma correction, edge detection), and route processed pixels to host CPUs over Gigabit Ethernet. The 773 user I/O pins accept multiple parallel image-data channels, while the 12 DSP blocks accelerate Sobel and Laplacian convolutions at line rate. Embedded TriMatrix memory holds image line buffers without external SRAM, reducing BOM cost. Quartus II provides the Image Processing library for filter instantiation.

推薦

EP1S20F484C7 · Intel EP1S25F672C7 · Intel

💊

Medical Imaging Reconstruction

The EP1S40F1020C5DM supports CT, MRI, and ultrasound reconstruction pipelines where raw sensor data must be back-projected and filtered in real time. Its 28.8 GMACS DSP throughput handles back-projection kernels, and the 3,423 Kbits of embedded memory serves as on-chip sinogram buffer. Medical-equipment designers value the deterministic latency of FPGA pipelines over software-only reconstruction. Use the Altera Floating-Point Compiler library for IEEE-754 single-precision math.

推薦

EP1S40F1020C5AA · Intel EP1S30F1020C6N · Intel

📡

Software-Defined Radio Baseband

Software-defined radio (SDR) baseband processing uses the EP1S40F1020C5DM to implement digital down-conversion, channelization, and demodulation across multiple RF bands. The 6 PLLs synthesize independent sample-rate clocks for each antenna stream, and the DSP blocks perform polyphase filter banks and FFT-based channelization. The 1020-ball BGA exposes enough LVDS pairs for multi-channel ADC interfacing. Designers load new waveform personalities via JTAG or external Flash for mission flexibility.

推薦

EP1S25F1020I6N · Intel EP1S20F672I7N · Intel

推薦產品摘要

EP1S30F1020C6 Altera 用於： Telecom Base Station Channel Card EP1S25F1020C6N Altera 用於： Telecom Base Station Channel Card EP1S25F672C7 Intel 用於： HD Video Broadcast Encoder, Industrial Machine Vision Inspection EP1S20F672C7 Intel 用於： HD Video Broadcast Encoder, High-Speed Serial Protocol Bridge EP1S40F1020C5AA Intel 用於： Military Radar Front-End Processing, Medical Imaging Reconstruction EP1S30F1020I6 Intel 用於： Military Radar Front-End Processing EP1S60F1020C5 Intel 用於： ASIC Prototyping Platform EP1S40F1020C5 Intel 用於： ASIC Prototyping Platform EP1S25F780I6N Intel 用於： High-Speed Serial Protocol Bridge EP1S20F484C7 Intel 用於： Industrial Machine Vision Inspection EP1S30F1020C6N Intel 用於： Medical Imaging Reconstruction EP1S25F1020I6N Intel 用於： Software-Defined Radio Baseband EP1S20F672I7N Intel 用於： Software-Defined Radio Baseband

What is the difference between EP1S40F1020C5DM and EP1S40F1020C5?

The EP1S40F1020C5DM is a Mil-temp / extended-reliability designation of the EP1S40F1020C5 Stratix FPGA, both sharing the same 41,250 logic elements, 1020-ball BGA, and core silicon. According to the Altera Stratix Device Handbook, the "DM" suffix indicates a specific die revision or screening grade applied during manufacturing, while the base EP1S40F1020C5 ships in commercial temp range. Both parts are pin-compatible in the 1020-FBGA package and can substitute on the same PCB, subject to operating-temperature verification.

How many logic elements does EP1S40F1020C5DM have?

The EP1S40F1020C5DM integrates 41,250 logic elements organized into 4,125 logic array blocks (LABs), along with 3,423 Kbits of TriMatrix embedded memory. This density places it in the mid-range of the original Stratix family, above the EP1S25 (25,660 LE) and below the EP1S60 (57,120 LE). For comparison, contemporary Stratix II (90 nm) and Stratix III (65 nm) devices offer higher logic density at lower core voltages.

What package does EP1S40F1020C5DM use?

The EP1S40F1020C5DM is housed in a 1020-ball FineLine BGA measuring 33 mm x 33 mm with a 1.0 mm ball pitch. This high-pin-count BGA is required to expose all 773 user I/O pins plus dedicated configuration, clock, JTAG, and power pins. The fine pitch demands PCB manufacturing with microvia or laser-drilled via technology for reliable fanout routing.

Is EP1S40F1020C5DM still in production?

The EP1S40F1020C5DM and the broader Stratix (non-II/III) family are listed as obsolete by Intel/Altera. According to distributor data retrieved 2026-09-07, the part is available only through authorized aftermarket stockists such as Rochester Electronics, Avnet, and smaller independent distributors. Lead times for new orders vary widely - check current distributor inventory before committing to a design-in, and consider migrating to Cyclone IV/V or Stratix V for new designs.

How much does EP1S40F1020C5DM cost?

As of 2026-09-07, EP1S40F1020C5DM unit pricing is approximately $245-$285 at quantities of 1-100 pieces on the secondary market, with higher volumes pulling price into the $198-$220 range. Pricing for obsolete FPGAs fluctuates with inventory cycles, so contact authorized distributors like Rochester Electronics or Avnet for current quotes. For new designs, an active Altera/Intel FPGA such as Cyclone IV or Cyclone 10 LP is typically less expensive and fully supported.

Where can I download the EP1S40F1020C5DM datasheet?

The EP1S40F1020C5DM datasheet is hosted as part of the Altera Stratix Device Handbook, Volume 1, available on the Alldatasheet archive (alldatasheet.com) and the Intel FPGA support archive. Search the legacy Altera handbook by device family, not exact MPN, because the original datasheets were issued at the family level. Note that Intel's online Resource Center may only host Stratix II and later datasheets; older Stratix (EP1S) datasheets live in archived locations.

What is the best drop-in replacement for EP1S40F1020C5DM?

The closest pin-compatible drop-in replacements for EP1S40F1020C5DM are other EP1S40F1020-family variants in the 1020-ball BGA, such as EP1S40F1020C5AA (industrial screening) and EP1S40F1020C5 (commercial). These share identical logic, memory, DSP, and pinout. For modern designs, consider Stratix II EP2S60F1020 (60K LE) or Stratix III EP3SE50F780 as functional upgrades that require PCB rework because they use different BGA pin maps - they are not drop-in.

What is the difference between EP1S40F1020C5DM and Stratix II EP2S60F1020C5?

EP1S40F1020C5DM is a first-generation Stratix device with 41,250 LE, 1.5 V core, and 0.13 µm process, while the EP2S60F1020C5 is a Stratix II device with 60,440 LE, 1.2 V core, and 90 nm process. Both share the 1020-ball BGA package family but have different pin maps and ball assignments, so they are NOT pin-compatible drop-in replacements. The Stratix II part delivers higher logic density and lower power but requires PCB redesign.

Does EP1S40F1020C5DM support DDR or QDR memory interfaces?

Yes, EP1S40F1020C5DM supports DDR SDRAM, DDR2 SDRAM, QDR, QDRII, and RLDRAM memory interfaces via dedicated DQS phase-shift circuitry and up to 12 PLLs. The maximum supported memory clock frequency depends on I/O standard and speed grade - C5 speed grade is mid-tier for the family. Designers use the Altera DDR/DDR2/DDR3 Memory Controller MegaCore IP in Quartus II to instantiate the physical layer and controller.

Can EP1S40F1020C5DM be used for ASIC prototyping?

Yes, EP1S40F1020C5DM is widely used for ASIC prototyping because its 41,250 LE and 3,423 Kbits of TriMatrix memory can map sizeable RTL designs, and the Stratix architecture supports incremental compile for multi-engineer team-based flows. Designers typically use Synopsys Design Compiler or Synplify Premier synthesis targeting Stratix, then place-and-route in Quartus II. For very large ASIC designs, multiple FPGAs can be wired together with board-level partitioning.

What is the maximum user I/O count on EP1S40F1020C5DM?

EP1S40F1020C5DM exposes 773 user I/O pins, distributed across multiple VCCIO banks on the 1020-ball BGA. The actual usable I/O count is lower than the package ball count because some balls are dedicated to VCCINT, VCCIO, GND, configuration, JTAG, PLL analog supply, and clock inputs. Per the Stratix Device Handbook, the device supports up to 45 high-speed LVDS channels in C5 speed grade.

What FPGA configuration mode should I use for EP1S40F1020C5DM?

EP1S40F1020C5DM supports passive serial (PS), passive parallel synchronous (PPS), passive parallel asynchronous (PPA), and JTAG configuration. The fastest configuration time is achieved via PPA mode using an 8-bit Flash memory such as Altera EPC16 or EPC64. JTAG is recommended for prototype programming and boundary-scan test, while PPS is the most common production mode using a low-cost parallel Flash.

Is EP1S40F1020C5DM RoHS compliant?

RoHS compliance status for EP1S40F1020C5DM is not stated in the verified web data and must be confirmed against the original Altera material declaration. First-generation Stratix FPGAs were released in 2002-2003, before RoHS became mandatory in 2006, so older date codes may be non-compliant. Contact your distributor for a specific date-code RoHS certificate if compliance is required for the target market.

What design tools support EP1S40F1020C5DM?

EP1S40F1020C5DM is supported by Altera Quartus II design software (legacy, not the newer Quartus Prime). Specifically, Quartus II version 9.1 was the last release to fully support first-generation Stratix (EP1S) devices. Altera recommends Quartus II Service Pack 2 or later for the most stable synthesis and timing closure results. Existing design files (.qpf, .qsf) can be migrated directly, but IP MegaCores targeting newer FPGA families will not generate.

What are typical applications for EP1S40F1020C5DM?

EP1S40F1020C5DM is commonly used in telecom base-station channel cards, HD video broadcast encoders, military radar and signal-intelligence front ends, high-speed serial protocol bridges (PCI Express Gen1, Gigabit Ethernet, RapidIO), industrial machine-vision systems, and ASIC prototyping platforms. Its combination of DSP blocks, high I/O count, and embedded memory makes it especially suited to applications that mix parallel data acquisition with on-chip DSP filtering.

工程參考資料，適用於 EP1S40F1020C5DM — 比較、設計指引及合規資訊。

選型指南

Choose the EP1S40F1020C5DM when you need a specific die-revision/screening-grade Stratix FPGA in the 1020-ball FineLine BGA for a maintenance or legacy-production environment with documented traceability requirements. For most other Stratix use cases, prefer the standard EP1S40F1020C5 (commercial temp) for lowest cost and shortest lead time, or EP1S40F1020C5AA (industrial -40C to +100C) for harsh-environment deployment. If your board is already laid out for the 956-ball BGA footprint, the EP1S40B956C6N delivers the same 41,250 LE logic density at lower cost but with reduced user I/O (683 vs 773). New designs should generally migrate to a Stratix II/III/V or Cyclone IV/V equivalent for active product support and lower power.

與替代品比較

參數	本產品	EP1S40F1020C5	EP1S40F1020C5AA	EP1S40B956C6N	EP1S40B956C6
Package	1020-ball FineLine BGA (33 mm x 33 mm, 1.0 mm pitch)	1020-ball FineLine BGA - same	1020-ball FineLine BGA - same	956-ball BGA (different)	956-ball BGA (different)
Brand	Intel (formerly Altera)	Intel (same brand)	Intel (same brand)	Intel (same brand)	Intel (same brand)
Logic Elements	41,250	41,250	41,250	41,250	41,250
Embedded Memory	3,423 Kbits	3,423 Kbits	3,423 Kbits	3,423 Kbits	3,423 Kbits
User I/O	773	773	773	683 (956-ball BGA reduces I/O)	683
DSP Blocks	12	12	12	12	12
Core Voltage	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V
Operating Temperature	Commercial (0C to +85C, DM suffix)	Commercial (0C to +85C)	Industrial (-40C to +100C)	Industrial	Commercial

主要差異化特點

DM suffix indicates specific die revision or screening grade (對比EP1S40F1020C5)
Industrial temperature option available in same 1020-ball BGA footprint (對比EP1S40F1020C5AA)
Higher user I/O count than 956-ball BGA package variant (對比EP1S40B956C6N)

設計說明

The EP1S40F1020C5DM 1020-ball FineLine BGA requires a multilayer PCB with at least 6 layers (4 routing + 2 ground planes). Use 1.0 mm ball pitch PCB technology with microvia or laser-drilled via fan-out for reliable BGA assembly. Decoupling capacitors must be placed within 5 mm of each power pin: 0.1 µF X7R for every VCCINT/VCCIO pair, plus bulk 22 µF tantalum capacitors near each power-rail entry point. Estimated via-count requirement: 4-6 vias per power ball, all stitching to inner ground planes for thermal dissipation.

Estimated thermal analysis: at typical Stratix EP1S40 utilization (50% logic switching, 50% memory, 50% I/O toggling) at 200 MHz, the device dissipates 4-6 W. The 1020-ball BGA theta_JA is approximately 8 C/W with the recommended 33 mm x 33 mm PCB footprint, giving a 32-48 C junction temperature rise above ambient. A heatsink is recommended for closed-enclosure designs but generally not required for cards with forced-air cooling. Place thermal vias directly under the BGA's exposed thermal pad row to improve conduction to the inner ground plane.

First-generation Stratix FPGAs require Quartus II (legacy), NOT Quartus Prime - attempting to open an EP1S design in Quartus Prime 18.0+ will fail because Intel dropped support for the EP1S family. Maintain a Quartus II 9.1 installation with Service Pack 2 for any active EP1S project. Also note: the EP1S40F1020C5DM is obsolete per Intel's product lifecycle; design teams should plan a migration path to Cyclone IV/V or Stratix V before the part is no longer obtainable.

合規資訊

RoHS

Unknown

REACH

Unknown

AEC-Q100

Not Applicable

無鉛

Unknown

無鹵

Unknown

衝突礦產

Unknown

RoHS/REACH status not stated in verified web data. Original Altera date codes from 2002-2006 may be pre-RoHS; verify with distributor for specific date-code compliance certificates. AEC-Q100 not applicable - this is an industrial/commercial FPGA, not an automotive-grade part.

資料驗證日期： 2026-09-07 — 資料由 XAIPART 元件工程團隊驗證及整理

來源： Manufacturer Datasheet, Distributor, Distributor, Manufacturer Datasheet, Distributor, Distributor, Distributor