EP1S40F1020C6 vs EP1S40F1020C5DM 比較

詳細並排比較 EP1S40F1020C6 由 Altera 與 EP1S40F1020C5DM 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP1S40F1020C6 EP1S40F1020C5DM
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family Stratix (original, EP1S) —
Logic Elements (LE) 41,250 —
Logic Array Blocks (LABs) 4,125 —
Embedded Memory Bits 3,423,744 bits (TriMatrix: M512 + M4K + M-RAM) —
Maximum User I/O 773 —
封裝 1020-BBGA, FC-FBGA, 33 x 33 mm, 1.0 mm pitch 1020-ball FineLine BGA (33 mm x 33 mm, 1.0 mm pitch)
Process Technology 0.13 µm CMOS 0.13 µm CMOS
Core Voltage 1.5 V —
工作溫度 0 °C to +85 °C (commercial) 0C to +85C (commercial)
Maximum Frequency 450.05 MHz —
Supply Voltage (Core) 1.5 V —
I/O Standards LVTTL, LVCMOS, LVDS, SSTL, HSTL, PCI, PCI-X —
安裝類型 Surface Mount (FCBGA) Surface Mount (BGA)
MSL 等級 [DATA_NEEDED: MSL rating from datasheet] [DATA_NEEDED: MSL level]
RoHS 狀態 [DATA_NEEDED: RoHS status from official datasheet] [DATA_NEEDED: RoHS status]
Product Type — FPGA - Field Programmable Gate Array
Series — Stratix
Logic Elements — 41,250
Embedded Memory — 3,423 Kbits TriMatrix
User I/O Count — 773
Number of LABs/CLBs — 4125
DSP Blocks — 12 (up to 28.8 GMACS at 200 MHz)
Number of PLLs — 6 (8 outputs each)
Number of Clock Networks — 16
Core Voltage VCCINT — 1.5 V
I/O Voltage VCCIO — 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-dependent)
Configuration Modes — PS, PPS, PPA, JTAG

資料表與資源

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