EP1S80F1020C6 vs EP1S80F1020C7 比較
詳細並排比較 EP1S80F1020C6 由 Intel 與 EP1S80F1020C7 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1S80F1020C6 | EP1S80F1020C7 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Series | Stratix | Stratix |
| Logic Elements | 79,040 | 79,040 |
| Total RAM Bits | 7,427,520 | — |
| Number of Logic Blocks / LABs | 9,191 | — |
| Number of I/O Pins (max) | 773 user I/O | — |
| Number of Pins / Balls | 1020 | — |
| Package Type | FC-FBGA (flip-chip fine-pitch BGA), 33 x 33 mm, 1.0 mm pitch | FBGA-1020 (33 x 33 mm, 1 mm pitch) |
| Process Technology | 130 nm CMOS | 1.5 V, 0.13 um CMOS |
| Core Supply Voltage (VCCINT) | 1.5 V nominal (1.425 V to 1.575 V) | 1.425 V to 1.575 V |
| Speed Grade | C6 | — |
| Operating Temperature (Commercial) | 0 C to +85 C | — |
| 安裝類型 | Surface Mount | Surface Mount (BGA) |
| Maximum Internal Clock Frequency | 450.05 MHz | — |
| Family Description | FPGA - Field Programmable Gate Array | — |
| Embedded Memory | TriMatrix (three block sizes, true/simple dual-port) | — |
| Configuration Interface | JTAG (IEEE 1149.1) + serial/parallel configuration device | — |
| Design Tool | Quartus II (legacy, Stratix family) | — |
| RoHS 狀態 | [DATA_NEEDED: rohs status] | Compliant (lead-free FBGA) |
| 濕度敏感等級 (MSL) | [DATA_NEEDED: MSL rating] | — |
| System Gates (typical) | — | 7,427,520 |
| Logic Array Blocks (LABs) | — | 7,904 |
| User I/O Pins | — | 773 |
| Total Package Pins | — | 1020 (ball) |
| 工作溫度 | — | 0 C to 85 C (Commercial) |
| Logic Family | — | CMOS, SRAM-based configuration |
| Configuration Modes | — | Passive Serial (PS), Fast Passive Parallel (FPP), JTAG |
| PLLs | — | 12 (per datasheet family) |
| Memory | — | TriMatrix embedded SRAM blocks |
| DSP Blocks | — | Dedicated hardware multipliers/accumulators |