EP1SGX10DF672C7N vs EP1SGX25DF67216 比較

詳細並排比較 EP1SGX10DF672C7N 由 Intel 與 EP1SGX25DF67216 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP1SGX10DF672C7N EP1SGX25DF67216
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 Obsolete
Product Type Field Programmable Gate Array (FPGA) —
Device Family Stratix GX —
Logic Cells 10,570 cells —
User I/O 362 I/O —
Logic Family CMOS —
Process Technology 130 nm —
供應電壓 1.5 V —
封裝 672-Ball FC-FBGA 672-ball FineLine BGA (DF672)
Alternative Package Description FBGA-1020 —
Package Body 33 mm x 33 mm —
Ball Pitch 1 mm —
Listed Frequency Figure 4,385.97 MHz —
工作溫度 0 C to 85 C Industrial, -40C to +100C (I-suffix family)
安裝類型 Surface Mount Surface Mount (BGA)
DigiKey Product Category FPGAs (Field Programmable Gate Array) —
RoHS 狀態 unknown Lead-free / RoHS compliant (per Altera product family documentation)
REACH Status unknown —
AEC-Q100 Status not_applicable —
Family — Stratix GX
Logic Elements — 25,660
Total RAM Bits — 1,944,576
Embedded Multipliers (18x18) — [DATA_NEEDED: 18x18 multiplier count]
Number of PLLs — 4
Number of Transceiver Channels — 8 (4 in each of 2 banks)
Max Transceiver Data Rate — 3.1875 Gbps per channel
Min Transceiver Data Rate — 500 Mbps
Core Supply Voltage — 1.5 V
Auxiliary Supply Voltage — 3.3 V
I/O Supply Voltage — 1.5 V / 1.8 V / 2.5 V / 3.3 V (per bank)
Maximum User I/O Pins — [DATA_NEEDED: user I/O count for DF672 package]
On-Die Termination — Yes, 100-ohm differential
Pre-emphasis / Equalization — Programmable (transmitter pre-emphasis; receiver adaptive equalization)
Configuration Schemes — Passive serial, fast passive parallel, JTAG, Altera enhanced configuration

資料表與資源

瀏覽所有產品 建立 BOM 索取報價