EP1SGX25DF1020C6ES vs EP1SGX25DF1020C6ESL 比較
詳細並排比較 EP1SGX25DF1020C6ES 由 Altera 與 EP1SGX25DF1020C6ESL 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP1SGX25DF1020C6ESL - Stratix GX FPGA, 25K LE, 1020-BGA | Altera/Intel
EP1SGX25DF1020C6ESL Obsolete規格比較
| 參數 | EP1SGX25DF1020C6ES | EP1SGX25DF1020C6ESL |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Family | Stratix GX | Stratix GX |
| Logic Elements | 25660 cells | 25,660 |
| Configurable Logic Blocks (CLBs) | 2566 | — |
| Maximum User I/Os | 607 | — |
| Number of LABs/CLBs | 2566 | — |
| Total RAM Bits | [DATA_NEEDED: total RAM bits] | 1,944,576 bits |
| 工作溫度 | 0 C to 85 C | — |
| Supply Voltage (Core) | 1.5 V | — |
| Process Technology | 130 nm CMOS | — |
| Logic Family | CMOS | — |
| 封裝 | FBGA-1020, 33 mm × 33 mm, 1.00 mm pitch | 1020-BBGA (FineLine BGA) |
| 安裝類型 | Surface Mount | Surface Mount |
| Lead-Free | Yes | — |
| RoHS 狀態 | [DATA_NEEDED: confirm RoHS] | [DATA_NEEDED: RoHS status] |
| Configuration Interface | JTAG / Passive Serial / Passive Parallel | — |
| Embedded Transceivers | Yes (multi-gigabit) | — |
| DSP Blocks | Yes | Yes (embedded DSP blocks) |
| User I/O Pins | — | 607 |
| LABs/CLBs | — | 2,566 |
| Core Voltage | — | 1.5 V |
| 工作接面溫度 | — | 0 C to 85 C |
| Configuration Method | — | Passive Serial / Fast Passive Parallel / JTAG |
| Process Node | — | 0.13 um CMOS |
| Transceivers | — | Embedded multi-gigabit transceivers (per Stratix GX family) |
| Speed Grade | — | C6 |
| I/O Standards Supported | — | LVTTL, LVCMOS, SSTL, HSTL, LVDS (per family) |