EP1SGX25DF800C5N vs EP1SGX25DF672C5N 比較

詳細並排比較 EP1SGX25DF800C5N 由 Intel 與 EP1SGX25DF672C5N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP1SGX25DF800C5N EP1SGX25DF672C5N
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family Stratix GX —
Device Logic Elements 25,660 (typical) —
Transceiver Channels 8 (full-duplex) —
Maximum Transceiver Data Rate 3.1875 Gbps per channel —
Process Technology 130 nm 130 nm CMOS
Supply Voltage (Core) 1.5 V typical 1.5 V (1.425 V to 1.575 V)
封裝 FBGA-800 (FineLine BGA, 31x31 mm) —
Speed Grade C5 (commercial) C5
工作溫度 0C to +85C (commercial) 0 C to 85 C (Commercial)
Lead-Free / RoHS Status Lead-free (N suffix) —
On-Chip Memory (TriMatrix) Approx. 2 Mbits total —
PLLs Up to 40 (device-wide) —
Embedded 8b/10b Encoder/Decoder Yes (one per transceiver channel) —
PCI Express Hard IP x1, x4 endpoints supported —
DSP Blocks Embedded multiplier blocks (family-wide) 10 (dedicated 18x18 multipliers)
安裝類型 Surface Mount (BGA) Surface Mount (FBGA)
MSL 等級 [DATA_NEEDED: MSL Level] —
Development Software Quartus II (legacy) —
Series — Stratix GX
Logic Elements — 25,660 LE
User I/O Count — 455
Total RAM Bits — 1,944,576 bits
Transceiver Data Rate — Up to 3.1875 Gbps
Number of Transceivers — 20
Package Type — 672-ball Flip-Chip BGA (FBGA-672)
Package Dimensions — 27 mm x 27 mm, 1.0 mm pitch
Configuration Modes — PS, PPS, FPP, JTAG
Lead Free / RoHS — Lead free per Altera/Intel datasheet

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