EP1SGX25FF1020C6 vs EP1SGX25FF1020I7 比較

詳細並排比較 EP1SGX25FF1020C6 由 Intel 與 EP1SGX25FF1020I7 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。

Intel

EP1SGX25FF1020C6 - Stratix GX FPGA 25,660 LE 607 I/O FBGA-1020 | Intel

EP1SGX25FF1020C6 Obsolete

Altera

EP1SGX25FF1020I7 Obsolete

參數	EP1SGX25FF1020C6	EP1SGX25FF1020I7
品牌	Intel	Altera
類別	FPGA & CPLD	FPGA & CPLD
生命週期狀態	Obsolete	Obsolete
Family	Stratix GX	Stratix GX
Series	Stratix GX	EP1SGX25
Logic Family	CMOS	—
Logic Elements / Cells	25,660	—
Number of LABs	2,566	—
Total Memory Bits	1,944,576 (1.94 Mbit, TriMatrix)	—
User I/O Count	607	—
腳位數	1020	—
Package Type	FBGA-1020 (FC-FBGA)	—
Package Dimensions	33 x 33 mm	—
Ball Pitch	1.0 mm	—
Core Supply Voltage	1.5 V	1.5 V
工作溫度	0 °C to 85 °C (Commercial)	—
Speed Grade	C6	7 (highest production grade)
安裝類型	Surface Mount	Surface Mount (FC-FBGA)
RoHS 狀態	Non-Compliant (legacy Altera era)	[DATA_NEEDED: RoHS compliance]
Lead Free	Yes	—
Logic Cells	—	25,660
Configurable Logic Blocks (CLBs)	—	2,566
Process Technology	—	130 nm CMOS
封裝	—	FC-FBGA-1020 (Flip-Chip Fine-pitch BGA)
Number of Terminals / Balls	—	1020
Terminal Form	—	Ball
Temperature Grade (suffix 'I')	—	Industrial
Terminal Pitch	—	[DATA_NEEDED: terminal pitch]
Combinatorial Delay per CLB	—	9.48 ns (per Microchip USA listing)
Combinatorial Delay Variant	—	[DATA_NEEDED: tPD per CLB variant speed grade]
Maximum Internal Clock Frequency	—	[DATA_NEEDED: max Fmax in MHz per speed grade]
Embedded Transceivers	—	Yes (Stratix GX feature)
Configuration Method	—	SRAM-based (volatile, requires configuration at power-up)
MSL 等級	—	[DATA_NEEDED: MSL level]