EP1SGX25FG672C7 vs EP1SGX25DF672C7 比較
詳細並排比較 EP1SGX25FG672C7 由 Altera 與 EP1SGX25DF672C7 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1SGX25FG672C7 | EP1SGX25DF672C7 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Stratix GX | Stratix GX |
| Series | Stratix | Stratix GX |
| Logic Elements (LE) | 25,660 | 25,660 |
| Total RAM Bits | 1,944,576 bits | 1,944,576 |
| User I/O Pins | 455 | — |
| Embedded Transceivers | Yes (multi-gigabit, up to 3.125 Gbps) | Yes (GX family) |
| Number of Transceivers | [DATA_NEEDED: exact transceiver count] | — |
| PLLs | 4 | — |
| Global Clocks | 16 | — |
| 封裝 | 672-pin FineLine BGA (FG672) | 672-FBGA (27 × 27 mm, 1.0 mm pitch) |
| 工作溫度 | 0C to +85C (commercial, speed grade C7) | 0 °C to +85 °C (Commercial) |
| Core Voltage | 1.5 V | — |
| Process Technology | 0.13 micron | 0.13 µm CMOS, SRAM-based |
| 安裝類型 | Surface Mount | Surface Mount |
| Speed Grade | 7 (commercial) | C7 (moderate Fmax bin) |
| Configuration Method | SRAM-based, JTAG/AS/PS supported | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | — |
| 生命週期狀態 | Obsolete (per Altera/Intel product discontinuance notices) | — |
| Logic Array Blocks (LABs) | — | 2,566 |
| User I/O Count | — | 455 |
| Embedded DSP Blocks | — | 14 |
| Core Supply Voltage | — | 1.425 V to 1.575 V (1.5 V nominal) |
| Lead Free / RoHS | — | Lead-Free, RoHS Compliant |
| PLL Count | — | [DATA_NEEDED: PLL count] |