EP20K1000CF33C9ES vs EP20K1000CF33C8ES 比較
詳細並排比較 EP20K1000CF33C9ES 由 Altera 與 EP20K1000CF33C8ES 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K1000CF33C9ES | EP20K1000CF33C8ES |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Family | APEX-20KC | APEX (Advanced Programmable Embedded Matrix) |
| Manufacturer | Intel (formerly Altera) | — |
| Typical Gate Count | 1,000,000 system gates | — |
| Logic Elements | 38,400 | — |
| Logic Array Blocks (LABs) | 3,840 | — |
| Embedded System Blocks (ESBs) | 212 | Dual-port RAM / ROM / CAM |
| Total Embedded RAM Bits | 327,680 bits | — |
| Maximum User I/O Pins | 708 | — |
| 封裝 | 1,020-ball FineLine BGA (FBGA) | 1020-ball FC-FBGA (Flip-Chip Fine-pitch BGA) |
| Speed Grade | C9 | C8 (Commercial) |
| 工作溫度 | 0 C to +85 C (commercial) | 0 °C to +85 °C (Commercial) |
| Process Technology | 0.18 um CMOS | 0.15 µm CMOS |
| Logic Element Architecture | 4-input LUT with dedicated carry chain | — |
| Maximum Embedded RAM per ESB | 32,768 bits (dual-port, FIFO support) | — |
| Phase-Locked Loops | Up to 4 enhanced PLLs | — |
| MultiVolt I/O Support | 1.8V / 2.5V / 3.3V / 5.0V | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Configuration Method | Passive serial / Passive parallel / JTAG | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free finish status] | unknown |
| Series | — | APEX 20KC |
| System Gates | — | 1,000,000 |
| Logic Elements / Cells | — | 38,400 |
| Embedded Memory Bits | — | 327,680 |
| Maximum User I/O | — | 708 |
| 安裝類型 | — | Surface Mount (BGA) |
| Core Supply Voltage | — | 1.8 V |
| Maximum Toggle Frequency | — | 301.21 MHz |
| Architecture | — | MultiCore (LUT + Embedded System Blocks) |
| Number of PLLs | — | 4 |
| Programming Interface | — | JTAG (IEEE 1149.1) - serial via Altera Quartus |