EP20K1000EBC652-2X vs EP20K100EBC652-2X 比較
詳細並排比較 EP20K1000EBC652-2X 由 Altera 與 EP20K100EBC652-2X 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP20K1000EBC652-2X - 1M Gate APEX-20KE FPGA, 488 I/O, 652-BGA | Altera (Intel)
EP20K1000EBC652-2X Nrnd規格比較
| 參數 | EP20K1000EBC652-2X | EP20K100EBC652-2X |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | APEX-20KE | APEX 20KE |
| Device Logic Elements | 38,400 | — |
| Typical Gates | 1,000,000 system gates | 100,000 |
| Embedded Memory Bits | 327,680 bits | — |
| User I/O Pins | 488 | — |
| Maximum User I/O | 488 | — |
| Propagation Delay | 1.6 ns | — |
| Internal Maximum Frequency | 350 MHz | — |
| Logic Blocks / Macros | 2,560 macros | — |
| PLLs | 4 | — |
| Core Voltage | 1.8 V | — |
| Process Technology | 0.22 µm (some sources 0.15 µm) all-layer copper-metal CMOS | 0.18 µm CMOS, SRAM-based |
| 封裝 | 652-pin FCBGA / PBGA (45 x 45 mm, 1.27 mm pitch) | 652-ball BGA (EBC652) |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | 0 °C to +85 °C (commercial) | 0C to +85C (commercial) |
| Configuration Interface | JTAG (IEEE 1149.1), Passive Serial, Altera configuration | — |
| RoHS 狀態 | Compliant | [DATA_NEEDED: RoHS status] |
| Maximum System Gates | — | 263,000 |
| Logic Elements | — | 4,160 |
| Embedded System Blocks (ESBs) | — | 26 |
| Maximum RAM Bits | — | 53,248 |
| Maximum User I/O Pins | — | 246 |
| Supply Voltage - Core | — | 1.8 V |
| Supply Voltage - I/O | — | 1.8 V / 2.5 V / 3.3 V |
| Speed Grade | — | -2 (faster commercial) |
| Configuration Method | — | Passive Serial / Passive Parallel / JTAG (EPC) |
| Clock Resources | — | Up to 4 DLLs, multiple global clocks |