EP20K100FC324-2X vs EP20K100FC324-1V 比較

詳細並排比較 EP20K100FC324-2X 由 Altera 與 EP20K100FC324-1V 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP20K100FC324-2X EP20K100FC324-1V
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family APEX-20K —
Logic Elements 4,160 —
Typical Gates 100,000 —
Maximum System Gates 263,000 —
Maximum User I/O 252 —
Embedded RAM Bits 53,248 —
Operating Frequency (max) 200 MHz —
Propagation Delay 1.6 ns —
Process Technology 0.22 µm CMOS —
Core Supply Voltage 2.5 V —
I/O Supply Voltage 3.3 V (5 V tolerant I/O) —
封裝 324-ball FineLine BGA (FBGA) —
安裝類型 Surface Mount Surface Mount
工作溫度 0 °C to +85 °C (Commercial) 0C to +85C (commercial)
Configuration Interface JTAG (IEEE 1149.1) / Serial / Parallel —
RoHS 狀態 Compliant [DATA_NEEDED: RoHS compliance]
Series — APEX-20K®
Number of Logic Elements / Cells — 4160
Total RAM Bits — 53248
Number of Gates (typical) — 100000
Number of I/O — 252
Number of LABs/CLBs — [DATA_NEEDED: number of Logic Array Blocks]
Number of EABs — [DATA_NEEDED: number of Embedded Array Blocks]
Supply Voltage - Core (VCCINT) — 2.375 V to 2.625 V
Supply Voltage - I/O (VCCIO) — 3.0 V / 3.3 V / 5.0 V tolerant (per I/O standard)
Speed Grade — -1V (commercial)
封裝 / 外殼 — 324-FBGA (FineLine BGA, 19x19 mm)
Supplier Device Package — 324-FBGA
Number of PLLs — 4
I/O Standards Supported — LVCMOS, LVTTL, PCI, SSTL, GTL+, HSTL
Architecture — MultiCore (LUT + product-term + embedded memory)
Programming Interface — JTAG (IEEE 1149.1) / in-system

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