EP20K200CB356C7N vs EP20K200CB356C8N 比較

詳細並排比較 EP20K200CB356C7N 由 Intel 與 EP20K200CB356C8N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP20K200CB356C7N EP20K200CB356C8N
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family APEX 20KC APEX 20KC
Series EP20K200 EP20K200
System Gates 200,000 200,000
Logic Elements / Cells 8,320 —
Maximum Operating Frequency 3571.6 MHz (internal equivalent) —
Propagation Delay 1.48 ns —
User I/Os 263 —
Input Terminals 267 —
Supply Voltage (Nominal) 1.8 V —
Process Technology 0.15 um CMOS 0.15 um CMOS
工作溫度 0C to +85C (Commercial) —
封裝 356-ball PBGA (S-PBGA) 356-ball LBGA
安裝類型 Surface Mount —
Embedded Memory ESBs (dual-port RAM/ROM/FIFO) —
Clock Management PLL with up to 4 outputs —
JTAG Support Yes (IEEE 1149.1) —
In-System Programmable Yes —
RoHS 狀態 unknown [DATA_NEEDED: RoHS compliance]
Device Type — SRAM-based LUT FPGA
Logic Elements (Cells) — 8,320
Maximum Internal Frequency — 301.21 MHz
Propagation Delay (tpd) — 1.78 ns
Nominal Core Supply Voltage — 1.8 V
Core Supply Voltage Range — 1.71 V to 1.89 V
Number of User I/O Pins — 263
Number of Dedicated Inputs — 4
Total Macrocells / Output Functions — 263
Embedded Memory Bits — 106,496 bits
Number of PLLs — 4
MultiVolt I/O Support — 1.5 V / 1.8 V / 2.5 V / 3.3 V
Differential Signaling — LVDS
Configuration Interface — Serial / JTAG (IEEE 1149.1)
Operating Temperature (commercial "C") — 0 C to +85 C (TJ)
Terminal Finish ("N") — Lead-free / Pb-free
濕度敏感等級 (MSL) — [DATA_NEEDED: MSL rating]

資料表與資源

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