EP20K400BC652-1X vs EP20K400GC655-1 比較
詳細並排比較 EP20K400BC652-1X 由 Intel 與 EP20K400GC655-1 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 Obsolete規格比較
| 參數 | EP20K400BC652-1X | EP20K400GC655-1 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Series | APEX 20KE | EP20K400 |
| Family | APEX 20K | APEX 20K |
| Logic Elements / Cells | 16,640 | — |
| System Gates | 400,000 | — |
| Embedded Memory (bits) | 212,992 | — |
| Embedded Array Blocks (EABs) | 104 x 2,048 bits | — |
| Maximum User I/O | 502 | 502 |
| Dedicated Inputs | 4 | 6 |
| PLLs | 4 | — |
| DLLs | 4 | — |
| Maximum Frequency | 250 MHz | — |
| Propagation Delay (pin-to-pin) | 2.5 ns | — |
| Core Voltage | 2.5 V | — |
| Process Technology | 0.22 um CMOS | 0.22 µm CMOS |
| I/O Standard Support | LVTTL, LVCMOS, PCI, SSTL-2/3, LVDS | — |
| 封裝 | 652-ball PBGA (45 x 45 mm, 1.27 mm pitch) | 655-pin CPGA (Ceramic Pin Grid Array) |
| 安裝類型 | Surface Mount | Through-Hole |
| Programming Interface | IEEE 1149.1 JTAG | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status not stated in retrieved snippets] | Non-compliant (contains lead in ceramic package) |
| 工作溫度 | Industrial (per datasheet) | 0 °C to +85 °C (commercial) |
| Logic Elements | — | 16,640 |
| Maximum Gates | — | 1,052,000 |
| Typical Gates | — | 400,000 |
| Embedded System Blocks (ESBs) | — | 4 |
| Total RAM Bits | — | 212,992 |
| Core Supply Voltage | — | 2.5 V |
| I/O Supply Voltage | — | 3.3 V |
| Maximum Internal Frequency | — | 250 MHz |
| Propagation Delay | — | 2.5 ns |
| 腳位數 | — | 655 |
| Configuration Modes | — | Passive Serial, Passive Parallel Async, Passive Parallel Sync |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |