EP20K400EFC672-3N vs EP20K400FC672-3X 比較
詳細並排比較 EP20K400EFC672-3N 由 Intel 與 EP20K400FC672-3X 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K400EFC672-3N | EP20K400FC672-3X |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | 最後購買 |
| Family | APEX 20KE | — |
| Series | APEX 20K | — |
| Device Type | FPGA - Field Programmable Gate Array | — |
| System Gates | 1,052,000 | — |
| Logic Elements | 16,640 | — |
| Logic Array Blocks (LABs) | 1,664 macros | — |
| Embedded RAM (EAB/ESB bits) | 212,992 bits | — |
| User I/O Pins | 488 | — |
| 封裝 | 672-BBGA (FC-FBGA) | 672-ball FC-FBGA (Fine-pitch Chip-Scale BGA) |
| 腳位數 | 672 | — |
| Propagation Delay | 2.5 ns | — |
| Core Supply Voltage | 1.71 V to 1.89 V (1.8 V nominal) | 2.5 V |
| I/O Supply Voltage | 2.5 V | — |
| 工作溫度 | 0 °C to +85 °C (commercial) | 0 °C to 85 °C (commercial) |
| Speed Grade | -3 | -3X |
| Technology | CMOS, 0.18 µm (per APEX 20KE family) | CMOS 0.22 µm |
| PLL Count | 4 | — |
| Architecture | MultiCore (LUT + Embedded System Blocks) | MultiCore (LUT + embedded CAM/RAM) |
| RoHS 狀態 | [DATA_NEEDED: specific RoHS status - likely non-compliant given part age] | [DATA_NEEDED: RoHS compliance] |
| Logic Family | — | APEX 20K |
| Device Sub-family | — | EP20K400 |
| Number of Gates | — | 400,000 (typical) |
| Logic Cells | — | 16,640 |
| Macros / Macrocells | — | 1664 |
| User I/Os | — | 502 |
| Dedicated I/O Lines | — | 496 |
| 最大時脈頻率 | — | 181.82 MHz |
| Typical Propagation Delay | — | 2.07 ns |
| Programming Interface | — | JTAG (IEEE 1149.1) / ByteBlaster / MasterBlaster |
| 安裝類型 | — | Surface Mount (BGA) |