EP20K400FC784-3 vs EP20K400FC784-2 比較

詳細並排比較 EP20K400FC784-3 由 Intel 與 EP20K400FC784-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP20K400FC784-3 EP20K400FC784-2
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family APEX 20K (MultiCore) APEX 20K
Typical Gates 400,000 —
Maximum System Gates 1,052,000 —
Logic Elements 21,168 16,640
Maximum RAM Bits 212,992 —
Embedded System Blocks (ESBs) 100 —
PLLs 4 —
User I/O Pins 488 —
封裝 784-ball FineLine BGA (FC) 784-Ball FineLine BGA (FC)
Speed Grade -3 -2 (industrial)
工作溫度 Commercial (0°C to +85°C) [DATA_NEEDED: exact Tj range]
I/O Standards MultiVolt I/O: 1.8V, 2.5V, 3.3V, 5.0V —
Core Voltage [DATA_NEEDED: core voltage] 2.5 V
Process Technology 0.18 µm CMOS 0.22 µm CMOS SRAM
Configuration Method Serial or parallel, SRAM-based —
RoHS 狀態 [DATA_NEEDED: RoHS status] [DATA_NEEDED: not confirmed in provided data]
MSL 等級 [DATA_NEEDED: MSL rating] 3 (per Partstack listing)
Lead-Free [DATA_NEEDED: lead-free status] —
Device Family Member — EP20K400C
Typical System Gates — 400,000
Maximum User I/O Pins — 488 (784-BGA)
Embedded RAM (ESB) — 212 Kbits
Maximum Block RAM — [DATA_NEEDED: block RAM organization per ESB]
Maximum Frequency (internal) — [DATA_NEEDED: fmax, datasheet-dependent]
MultiVolt I/O Voltage — 1.8 V / 2.5 V / 3.3 V
Supported I/O Standards — LVTTL, LVCMOS, PCI, SSTL-2, SSTL-3, GTL+, CTT
Configuration Mode — Serial / Parallel SRAM-volatile (external PROM required)
安裝類型 — Surface Mount (BGA)
Peak Reflow Temperature — 220 °C (per Partstack listing)
Hot Socketing — Supported
JTAG / Boundary-Scan — IEEE 1149.1 compliant

資料表與資源

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