EP20K400FI672-2 vs EP20K400FC672-1XGZ 比較
詳細並排比較 EP20K400FI672-2 由 Altera 與 EP20K400FC672-1XGZ 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP20K400FI672-2 - 400K Gates APEX-20K FPGA, 502 I/O, 672-FBGA | Altera
EP20K400FI672-2 ObsoleteIntel
EP20K400FC672-1XGZ - 400K Gate APEX-20KE FPGA, 502 I/O, 672-FBGA | Intel
EP20K400FC672-1XGZ Obsolete規格比較
| 參數 | EP20K400FI672-2 | EP20K400FC672-1XGZ |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX-20K | APEX-20KE |
| Logic Elements | 16640 | — |
| Maximum Gates | 400,000 gates | — |
| User I/Os | 502 | — |
| Embedded Memory Bits | 212992 | 212,992 |
| Number of Macros | 1664 | — |
| Process Technology | 0.22 µm CMOS | — |
| Core Supply Voltage | 2.5 V | 2.5 V |
| Maximum Internal Frequency | 200 MHz | — |
| Propagation Delay | 2.5 ns | 2.5 ns (per DigiChip listing) |
| 工作溫度 | 0 °C to +85 °C (Commercial) | 0C to +85C (commercial) |
| Package Type | 672-pin Fine-pitch Ball Grid Array (FBGA/FCBGA) | — |
| PLLs (Phase-Locked Loops) | 4 | — |
| Configuration Modes | JTAG, Passive Serial, Passive Parallel | — |
| RoHS 狀態 | Lead-free / RoHS Compliant | Unknown (legacy part, pre-dates widespread RoHS conversion) |
| 安裝類型 | Surface Mount (BGA) | Surface Mount |
| Logic Elements / Cells | — | 16,640 |
| System Gates | — | 400,000 (typical) |
| Maximum User I/O | — | 502 |
| 封裝 | — | 672-pin FBGA (Fine-pitch BGA) |
| Logic Family / Process | — | CMOS |
| Speed Grade | — | -1 (slowest commercial bin) |
| MSL 等級 | — | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |
| Configuration Method | — | JTAG / passive serial / passive parallel (per APEX-20KE handbook) |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, GTL+ (per APEX-20KE family datasheet) |