EP20K400GC655-1 vs EP20K400GC652-1XV 比較
詳細並排比較 EP20K400GC655-1 由 Intel 與 EP20K400GC652-1XV 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 Obsolete
規格比較
| 參數 | EP20K400GC655-1 | EP20K400GC652-1XV |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20K | APEX 20K |
| Series | EP20K400 | — |
| Logic Elements | 16,640 | — |
| Maximum Gates | 1,052,000 | — |
| Typical Gates | 400,000 | — |
| Embedded System Blocks (ESBs) | 4 | — |
| Total RAM Bits | 212,992 | — |
| Maximum User I/O | 502 | 502 |
| Dedicated Inputs | 6 | — |
| Process Technology | 0.22 µm CMOS | — |
| Core Supply Voltage | 2.5 V | 2.5 V |
| I/O Supply Voltage | 3.3 V | — |
| Maximum Internal Frequency | 250 MHz | — |
| Propagation Delay | 2.5 ns | 2.5 ns |
| 封裝 | 655-pin CPGA (Ceramic Pin Grid Array) | — |
| 腳位數 | 655 | — |
| 安裝類型 | Through-Hole | Surface Mount |
| 工作溫度 | 0 °C to +85 °C (commercial) | 0 C to +85 C |
| Configuration Modes | Passive Serial, Passive Parallel Async, Passive Parallel Sync | — |
| Boundary Scan | IEEE 1149.1 (JTAG) | — |
| RoHS 狀態 | Non-compliant (contains lead in ceramic package) | Compliant (lead-free, V suffix) |
| Logic Elements (Macros) | — | 1664 |
| Typical System Gates | — | 400,000 |
| Embedded SRAM | — | 212,992 bits |
| Logic Family | — | CMOS |
| Package Type | — | BGA-652 (thermally enhanced) |
| Speed Grade | — | -1 (standard) |
| Architecture | — | MultiCore (LUT + EAB + FastTrack interconnect) |
| Programming Interface | — | JTAG (IEEE 1149.1) / passive serial |