EP20K400GC655-2 vs EP20K400GI655-1V 比較

詳細並排比較 EP20K400GC655-2 由 Altera 與 EP20K400GI655-1V 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Intel
EP20K400GI655-1V EP20K400GI655-1V - APEX 20K 400K Gate FPGA, 655-pin CBGA | Intel

EP20K400GI655-1V - APEX 20K 400K Gate FPGA, 655-pin CBGA | Intel

EP20K400GI655-1V ⚠ 最後購買機會

規格比較

參數 EP20K400GC655-2 EP20K400GI655-1V
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete 最後購買
Series APEX-20KC —
Family APEX 20K APEX 20K
Device Type FPGA (Field Programmable Gate Array) —
System Gates 400,000 —
Logic Cells / Elements 16,640 —
Total RAM Bits 212,992 —
Maximum Internal Frequency 200 MHz —
Speed Grade -2 —
Process Technology 0.22 µm CMOS CMOS
Core Supply Voltage 2.5 V 2.5 V
I/O Supply Voltage 1.71 V to 1.89 V (MultiVolt) 2.5 V / 3.3 V
LVDS Support Yes —
PLLs 4 —
腳位數 655 —
Package Type 655-BCPGA (CPGA-655) CBGA-655 (Ceramic Ball Grid Array)
Package Dimensions 62.48 x 62.48 mm —
安裝類型 Through-Hole (CPGA) —
工作溫度 [DATA_NEEDED: operating temperature range] [DATA_NEEDED: industrial vs military grade]
RoHS 狀態 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED]
Typical Gates — 400,000
Logic Elements — 16,640
Maximum User I/O — 502
Dedicated Inputs — 4
Package Code (JESD-30) — S-CPGA-P655
Package Equivalence Code — SPGA655, 47x47
Propagation Delay — 2.5 ns
Configuration — In-system programmable via JTAG
Boundary Scan — IEEE 1149.1 JTAG
MSL 等級 — 1
Package Body Material — Ceramic

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