EP20K400GC655-2X vs EP20K400PI655-2X 比較
詳細並排比較 EP20K400GC655-2X 由 Altera 與 EP20K400PI655-2X 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EP20K400PI655-2X - APEX 20K 400K Gates FPGA, 655-Pin PQFP | Intel / Altera
EP20K400PI655-2X Obsolete規格比較
| 參數 | EP20K400GC655-2X | EP20K400PI655-2X |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20K | APEX 20K |
| Series | APEX-20KC® | — |
| Logic Elements / Cells | 16640 | — |
| System Gates | 400000 | — |
| Total RAM Bits | 212992 | — |
| Number of I/O | 496 | — |
| Number of Dedicated Inputs | 6 | — |
| Number of LABs/CLBs | [DATA_NEEDED: number of Logic Array Blocks] | — |
| Number of EABs | [DATA_NEEDED: number of Embedded Array Blocks] | — |
| Maximum Operating Frequency | 200 MHz | — |
| Process Technology | 0.22 µm CMOS | 0.18 um CMOS |
| Core Supply Voltage | 2.5 V | — |
| I/O Supply Voltage (MultiVolt) | 2.5 V / 3.3 V / 5 V | — |
| Package Type | 655-BCPGA (SPGA655) | — |
| Package Body Material | CERAMIC, metal-sealed cofired grid array | — |
| Package Dimensions | 47 x 47 mm | — |
| Peak Reflow Temperature | 220 °C | — |
| 安裝類型 | Through-hole (CPGA) | Surface Mount |
| Programmability | In-system, JTAG (IEEE 1149.1) | — |
| 工作溫度 | [DATA_NEEDED: temperature grade] | -40C to +85C (Industrial) |
| RoHS 狀態 | unknown | — |
| Device Series | — | EP20K400 |
| Speed Grade | — | -2X |
| Maximum Logic Elements | — | 16,640 |
| Maximum System Gates | — | 400,000 |
| Maximum RAM Bits | — | 166,400 |
| Embedded System Blocks (ESBs) | — | 104 |
| Maximum User I/O Pins | — | 488 |
| Maximum PLLs | — | 4 |
| 封裝 | — | PQFP-655 (Power Quad Flat Pack) |
| Core Voltage | — | 3.3 V |
| I/O Standards | — | LVTTL, LVCMOS, PCI, GTL+ |
| Configuration Method | — | Serial / Parallel / JTAG |
| Lead-Free / RoHS | — | [DATA_NEEDED: lead-free status] |
| 生命週期狀態 | — | Obsolete (legacy Altera APEX 20K family) |