EP20K400GI655-1V vs EP20K400GI655-1 比較
詳細並排比較 EP20K400GI655-1V 由 Intel 與 EP20K400GI655-1 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K400GI655-1V | EP20K400GI655-1 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Family | APEX 20K | APEX 20K |
| Typical Gates | 400,000 | 400000 |
| Logic Elements | 16,640 | 16640 |
| Maximum User I/O | 502 | 502 |
| Dedicated Inputs | 4 | 4 |
| Package Type | CBGA-655 (Ceramic Ball Grid Array) | Ceramic Pin Grid Array (CPGA-655) |
| Package Code (JESD-30) | S-CPGA-P655 | — |
| Package Equivalence Code | SPGA655, 47x47 | — |
| Process Technology | CMOS | — |
| Propagation Delay | 2.5 ns | 2.5 ns |
| Core Supply Voltage | 2.5 V | — |
| I/O Supply Voltage | 2.5 V / 3.3 V | — |
| Configuration | In-system programmable via JTAG | — |
| Boundary Scan | IEEE 1149.1 JTAG | — |
| 工作溫度 | [DATA_NEEDED: industrial vs military grade] | -40C to +85C (Industrial) |
| MSL 等級 | 1 | — |
| Package Body Material | Ceramic | — |
| RoHS 狀態 | [DATA_NEEDED] | Compliant |
| Device Series | — | EP20K400 |
| Technology | — | CMOS, SRAM-based |
| Total Terminals | — | 655 |
| JESD-30 Package Code | — | S-CPGA-P655 |
| Moisture Sensitivity Level | — | MSL 1 |
| Peak Reflow Temperature | — | 220 C |
| Programmability | — | In-system, JTAG boundary-scan (IEEE 1149.1) |
| Process Node | — | 0.18 micrometer CMOS |