EP20K400GI655-2V vs EP20K400GI655-1V 比較
詳細並排比較 EP20K400GI655-2V 由 Intel 與 EP20K400GI655-1V 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K400GI655-2V | EP20K400GI655-1V |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Family | APEX 20K | APEX 20K |
| Maximum Gates | 400,000 | — |
| Logic Elements | 16,640 | 16,640 |
| Embedded RAM Bits | 212,992 | — |
| User I/O Pins | 496 | — |
| Dedicated Inputs | 6 | 4 |
| 封裝 | SPGA-655 (ceramic, 47 x 47 mm) | — |
| Package Equivalence Code | SPGA655,47X47 | SPGA655, 47x47 |
| Process Technology | 0.18 µm CMOS | CMOS |
| Core Supply Voltage | 2.5 V (2.375 V to 2.625 V) | 2.5 V |
| I/O Supply Voltage | 3.3 V | 2.5 V / 3.3 V |
| Propagation Delay | 3.0 ns to 3.1 ns | 2.5 ns |
| 濕度敏感等級 (MSL) | 1 | — |
| Package Body Material | Ceramic | Ceramic |
| 工作溫度 | Industrial (per -2V speed grade) | [DATA_NEEDED: industrial vs military grade] |
| RoHS 狀態 | Non-compliant (ceramic SPGA, contains lead) | [DATA_NEEDED] |
| Typical Gates | — | 400,000 |
| Maximum User I/O | — | 502 |
| Package Type | — | CBGA-655 (Ceramic Ball Grid Array) |
| Package Code (JESD-30) | — | S-CPGA-P655 |
| Configuration | — | In-system programmable via JTAG |
| Boundary Scan | — | IEEE 1149.1 JTAG |
| MSL 等級 | — | 1 |