EP20K400GI655-2V vs EP20K400GI655-3 比較
詳細並排比較 EP20K400GI655-2V 由 Intel 與 EP20K400GI655-3 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K400GI655-2V | EP20K400GI655-3 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20K | APEX 20KE |
| Maximum Gates | 400,000 | — |
| Logic Elements | 16,640 | — |
| Embedded RAM Bits | 212,992 | — |
| User I/O Pins | 496 | — |
| Dedicated Inputs | 6 | 4 |
| 封裝 | SPGA-655 (ceramic, 47 x 47 mm) | 655-Pin PGA (Plastic/CPGA, square) |
| Package Equivalence Code | SPGA655,47X47 | — |
| Process Technology | 0.18 µm CMOS | CMOS, 2.5V core |
| Core Supply Voltage | 2.5 V (2.375 V to 2.625 V) | 2.5 V |
| I/O Supply Voltage | 3.3 V | 2.5 V or 3.3 V (MultiVolt I/O) |
| Propagation Delay | 3.0 ns to 3.1 ns | — |
| 濕度敏感等級 (MSL) | 1 | — |
| Package Body Material | Ceramic | — |
| 工作溫度 | Industrial (per -2V speed grade) | 0°C to 70°C (Industrial I grade) |
| RoHS 狀態 | Non-compliant (ceramic SPGA, contains lead) | [DATA_NEEDED: RoHS status] |
| Logic Elements / Cells | — | 16,640 |
| System Gates | — | 400,000 (maximum) |
| Maximum User I/O | — | 502 |
| Number of Terminals | — | 655 |
| JESD-30 Code | — | S-CPGA-P655 |
| Package Shape | — | Square |
| Form of Terminal | — | PIN/PEG (through-hole) |
| 安裝類型 | — | Through-Hole (Socket) |
| Speed Grade | — | -3 (slowest of the EP20K400 family) |
| Configuration Modes | — | Passive Serial, Passive Parallel Asynchronous, JTAG |
| Embedded Memory | — | Dual-port RAM via Embedded System Blocks (ESBs) |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |