EP20K600CF672C7ES vs EP20K600CF672C6 比較
詳細並排比較 EP20K600CF672C7ES 由 Altera 與 EP20K600CF672C6 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K600CF672C7ES | EP20K600CF672C6 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Series | APEX 20KC | — |
| Family | APEX 20K | APEX 20KC |
| Logic Elements / Cells | 24320 | — |
| System Gates | 600000 | — |
| Maximum User I/O | 504 | — |
| Maximum Input Lines | 508 | — |
| Number of Macrocells | 504 | — |
| Maximum Operating Frequency | 375.94 MHz (per FPGAkey listing) | — |
| Propagation Delay | 1.6 ns | — |
| Internal Reference Clock | 1666.6 MHz | — |
| Process Technology | 0.15 µm CMOS | 0.18 µm CMOS, 6 metal layers |
| Core Supply Voltage (VCCINT) | 1.8 V | — |
| Package Type | FC-FBGA | — |
| Pin / Ball Count | 672 | — |
| Grade Suffix | ES (engineering sample / extended screening) | — |
| 工作溫度 | [DATA_NEEDED: operating temperature grade] | 0 °C to +85 °C (commercial) |
| 安裝類型 | Surface Mount (BGA) | — |
| MSL 等級 | [DATA_NEEDED: MSL rating] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | Non-RoHS (legacy process) |
| Configuration Memory | SRAM-based (volatile) | — |
| Typical Gate Count | — | 600,000 gates |
| Logic Elements (LEs) | — | 24,320 |
| Embedded System Blocks (ESBs) | — | 160 (each 2,048 bits) |
| Maximum Embedded RAM | — | 311,296 bits (311 kbit) |
| Maximum User I/O Pins | — | 508 |
| 封裝 | — | 672-ball FineLine BGA (CF672) |
| Package Body Size | — | 27 mm × 27 mm |
| Speed Grade | — | -6 (C6) |
| Core Voltage | — | 1.8 V |
| I/O Standards Supported | — | LVCMOS, LVTTL, HSTL, SSTL, GTL+ |
| Embedded PLLs | — | 4 |
| Configuration Method | — | SRAM-based, JTAG, EPC16/EPC2 |