EP20K600CF672I8 vs EP20K600CF672I-8ES 比較
詳細並排比較 EP20K600CF672I8 由 Altera 與 EP20K600CF672I-8ES 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP20K600CF672I-8ES - APEX 20KC 600K-Gate FPGA, 672-BGA | Intel / Altera
EP20K600CF672I-8ES Obsolete規格比較
| 參數 | EP20K600CF672I8 | EP20K600CF672I-8ES |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KC |
| Device Type | SPLD / FPGA | — |
| Logic Elements / Cells | 24,320 | — |
| Macros (Logic Cells) | 2432 | — |
| Typical Gate Count | 600,000 gates | — |
| Embedded Memory | 311,296 bits | — |
| User I/Os | 488 to 508 | — |
| 腳位數 | 652 (functional) / 672 (BGA balls) | — |
| Propagation Delay (typical) | 1.48 ns | — |
| Internal Frequency (max) | [DATA_NEEDED: max internal frequency in MHz] | — |
| Core Supply Voltage | 1.8 V | — |
| Process Technology | 0.15 µm all-layer copper | 0.18 micron CMOS SRAM |
| 工作溫度 | 0 °C to +85 °C (Industrial) | -40C to +100C (Industrial) |
| Package Type | 672-ball BGA, 45 x 45 mm, 1.27 mm pitch | — |
| 安裝類型 | Surface Mount | — |
| RoHS 狀態 | Compliant per legacy product records | Non-compliant (legacy Altera leaded BGA process) |
| Configuration Interface | JTAG / Passive Serial | — |
| Design Tool | Quartus II (legacy MAX+PLUS II) | — |
| Logic Elements | — | 24,320 |
| Typical Gates | — | 600,000 (ASIC-equivalent) |
| Embedded Memory Bits | — | 311,296 |
| Maximum User I/O Pins | — | 508 |
| Embedded PLLs | — | 4 |
| Core Voltage | — | 1.8 V |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, SSTL, HSTL, GTL+ |
| Speed Grade | — | -8 (slower) |
| 封裝 | — | 672-ball BGA (FineLine BGA, 1.27 mm pitch) |
| Configuration Modes | — | Passive Serial, Fast Passive Parallel, Passive Parallel Asynchronous, JTAG |
| In-System Programmability | — | Yes (ISP via EPC16, EPC8, EPC4, EPC2, EPC1) |
| MSL 等級 | — | [DATA_NEEDED: moisture sensitivity level] |