EP2A25F672I-9 vs EP2A25F672C9 比較
詳細並排比較 EP2A25F672I-9 由 Intel 與 EP2A25F672C9 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP2A25F672I-9 | EP2A25F672C9 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | APEX II | APEX II |
| Logic Elements (typical) | 25,000 | — |
| Maximum System Gates | [DATA_NEEDED: maximum system gates] | — |
| Embedded System Blocks (ESB) Memory | 1,125 Kbits | — |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O pins] | — |
| Number of PLLs | 4 | — |
| Process Technology | 0.18 µm CMOS | 0.15 µm all-layer copper, up to 8 metal layers |
| Core Voltage | 1.5 V / 1.8 V (speed-grade dependent) | — |
| Operating Temperature Grade | Industrial (-40 °C to +100 °C junction) | — |
| Speed Grade | -9 | — |
| 封裝 | 672-pin FCBGA (FineLine BGA) | 672-ball FCBGA (FineLine BGA) |
| 安裝類型 | Surface Mount (BGA) | Surface Mount |
| 濕度敏感等級 (MSL) | 3 (per Vyrian listing) | — |
| Peak Reflow Temperature | 220 °C (per Vyrian listing) | — |
| Configuration Method | JTAG / serial configuration EPROM | — |
| Supported I/O Standards | LVTTL, LVCMOS, LVDS, PCI | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED] |
| Legacy Status | Obsolete - consult Altera / Intel FPGA archive for documentation | — |
| Logic Elements (LE) | — | Approximately 25,000 |
| Macro Cells | — | 2432 |
| User I/O | — | 492 |
| Package Dimensions | — | 27 mm x 27 mm |
| Ball Pitch | — | 1.0 mm |
| Logic Family | — | CMOS |
| Propagation Delay | — | 1.69 ns |
| 工作溫度 | — | 0°C to 85°C (Commercial) |
| 供應電壓 | — | [DATA_NEEDED: core VCC voltage] |
| I/O Standards | — | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL (multi-voltage 1.5/1.8/2.5/3.3 V) |
| Configuration | — | Passive Serial, Passive Parallel Synchronous, JTAG |
| Embedded Memory | — | ESBs for dual-port RAM, ROM, FIFO |