EP2A40F1020C7ES vs EP2A40F1020C9ES 比較
詳細並排比較 EP2A40F1020C7ES 由 Intel 與 EP2A40F1020C9ES 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP2A40F1020C9ES - APEX II FPGA 1.5M Gates 38400 Cells 366MHz | Altera
EP2A40F1020C9ES Obsolete規格比較
| 參數 | EP2A40F1020C7ES | EP2A40F1020C9ES |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX II | APEX II |
| Logic Elements | 38,400 | — |
| Typical Gates | 1,500,000 | — |
| Embedded Memory | 655,360 bits | Embedded System Blocks (ESBs) - RAM/ROM |
| Maximum User I/O | 735 | — |
| Maximum Frequency | 562 MHz | — |
| Process Technology | 0.15 µm CMOS, all-layer copper, up to 8 metal layers | 0.15 µm CMOS |
| Core Voltage | 1.5 V | — |
| 封裝 | 1020-pin FC-FBGA | 1020-pin FC-FBGA |
| Speed Grade | C7 (with ES enhanced speed suffix) | — |
| High-Speed Interface | 1 Gbps True-LVDS, LVPECL, PCML, HyperTransport | — |
| 工作溫度 | [DATA_NEEDED: commercial/industrial grade] | [DATA_NEEDED: operating temperature grade] |
| I/O Standards | LVTTL, LVCMOS, LVDS, LVPECL, PCML, HyperTransport, 1.5/1.8/2.5/3.3 V | LVDS and other high-speed standards (per family datasheet) |
| PLLs | Up to 8 (per datasheet family feature) | — |
| RoHS 狀態 | [DATA_NEEDED] | [DATA_NEEDED: RoHS status] |
| Programming Interface | JTAG (IEEE 1149.1), passive serial | — |
| 安裝類型 | Surface Mount (FC-FBGA) | Surface Mount |
| System Gates | — | 1.5 M |
| Logic Cells / Elements | — | 38,400 |
| Maximum Internal Clock Frequency | — | 366 MHz |
| Core Supply Voltage | — | 1.5 V |
| Package Type | — | Flip-Chip Fine-Pitch Ball Grid Array |
| RAM Support | — | Synchronous and asynchronous |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |