EP2A40F1020C9ES vs EP2A40F1020C8N 比較

詳細並排比較 EP2A40F1020C9ES 由 Altera 與 EP2A40F1020C8N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP2A40F1020C9ES EP2A40F1020C8N
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family APEX II —
System Gates 1.5 M —
Logic Cells / Elements 38,400 —
Maximum Internal Clock Frequency 366 MHz —
Process Technology 0.15 µm CMOS —
Core Supply Voltage 1.5 V —
封裝 1020-pin FC-FBGA —
Package Type Flip-Chip Fine-Pitch Ball Grid Array FC-FBGA, BGA-1020
安裝類型 Surface Mount Surface Mount
Embedded Memory Embedded System Blocks (ESBs) - RAM/ROM —
I/O Standards LVDS and other high-speed standards (per family datasheet) —
RAM Support Synchronous and asynchronous —
工作溫度 [DATA_NEEDED: operating temperature grade] 0 °C to 85 °C
RoHS 狀態 [DATA_NEEDED: RoHS status] unknown
Lead-Free [DATA_NEEDED: lead-free status] —
Product Type — Field-Programmable Gate Array (FPGA)
Device Family — APEX II
Logic Technology — CMOS
Logic Gates — 1.5 million
Logic Cells — 38,400
Nominal Supply Voltage — 1.5 V
Supply Voltage Range — 1.425 V to 1.575 V
User I/Os — 735
Package Terminal Count — 1,020 pins
Package Body Size — 33 mm x 33 mm
Ball Pitch — 1 mm
Reported Operating Frequency — 376 MHz
Alternative Reported Frequency — 562 MHz
Reported Propagation Delay — 1.78 ns
Alternative Reported Propagation Delay — 1.55 ns
Fabrication Process — 0.15 µm
Maximum Reported Metal Layers — 8 layers
Terminal Form — Ball
REACH Status — unknown
AEC-Q100 Qualification — unknown

資料表與資源

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