EP2A40F672C6 vs EP2A40F672C9 比較
詳細並排比較 EP2A40F672C6 由 Altera 與 EP2A40F672C9 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP2A40F672C6 | EP2A40F672C9 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Family | APEX II | APEX II |
| Device | EP2A40 | — |
| Logic Elements (typical) | 40,000 | — |
| Maximum System Gates | [DATA_NEEDED: maximum system gates] | — |
| Embedded System Blocks (ESBs) | [DATA_NEEDED: ESB count] | — |
| Maximum User I/O Pins | [DATA_NEEDED: max user I/O count] | — |
| 封裝 | 672-ball FineLine BGA (FBGA-672) | 672-BBGA, FC-FBGA (FineLine) |
| Speed Grade | C6 (commercial) | — |
| 工作溫度 | Commercial (0C to +85C) | 0 °C to 85 °C (commercial) |
| Process Technology | 0.18-micron CMOS | 0.15 µm all-layer copper, up to 8 metal layers |
| Configuration Memory | SRAM-based | — |
| JTAG Support | Yes (IEEE 1149.1) | — |
| PLL Support | Yes | — |
| 安裝類型 | Surface Mount (BGA) | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Lifecycle | Obsolete / EOL (per Intel/Altera product discontinuation notice) | — |
| Device Family | — | APEX II PLD |
| Logic Elements / Cells | — | 38,400 |
| System Gates | — | 1.5 M |
| Macros | — | 2,560 |
| User I/Os | — | 492 |
| 腳位數 | — | 672 |
| Package Size | — | 27 mm × 27 mm, 1 mm ball pitch |
| Core Voltage | — | 1.5 V |
| Logic Family | — | CMOS |
| Propagation Delay | — | 1.55 ns |
| Internal Speed Grade | — | 366 MHz |
| I/O Standards Supported | — | True-LVDS, LVPECL, PCML, HyperTransport |