EP2A40F672C8N vs EP2A40F672C6N 比較

詳細並排比較 EP2A40F672C8N 由 Intel 與 EP2A40F672C6N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP2A40F672C8N EP2A40F672C6N
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family APEX II APEX II
Series EP2A40 —
Logic Family CMOS —
System Gates 1.5 M —
Logic Elements / Cells 38,400 —
Maximum Operating Frequency 376 MHz —
Propagation Delay 1.55 ns —
Technology Node 0.15 µm —
Process Feature All-layer copper, up to 8 metal layers —
Nominal Supply Voltage (VCCINT) 1.5 V —
Supply Voltage Range 1.425 V to 1.575 V —
User I/Os 492 —
Number of Pins / Balls 672 —
Package Type FC-FBGA (FineLine BGA) —
Package Dimensions 27 x 27 mm —
Ball Pitch 1.0 mm —
LVDS Data Rate 1 Gbps —
Embedded PLLs 4 —
Programming Interface JTAG (IEEE 1149.1) —
Operating Temperature (Commercial) 0 °C to 85 °C —
Speed Grade C8 C6 (per part number suffix)
RoHS 狀態 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Logic Elements — 40,000
Maximum System Gates — 1,125,000
Embedded RAM Bits — 442,368
Embedded System Blocks (ESBs) — 160
Maximum User I/O Pins — [DATA_NEEDED: maximum user I/O count]
Core Voltage — 1.5 V
I/O Standards Supported — LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL, 1.8V/2.5V/3.3V/5V
封裝 — 672-ball FineLine BGA
工作溫度 — Commercial (0C to +85C)
Configuration Methods — Passive Serial, Passive Parallel, JTAG
安裝類型 — Surface Mount
Process Technology — SRAM-based, 0.18 um (per family datasheet)
PLL Count — [DATA_NEEDED: PLL count]

資料表與資源

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