EP2A40F672C9 vs EP2A40F672C6N 比較

詳細並排比較 EP2A40F672C9 由 Altera 與 EP2A40F672C6N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EP2A40F672C9 EP2A40F672C9 - APEX II FPGA 1.5M Gates 38400 Cells 672-BGA | Altera

EP2A40F672C9 - APEX II FPGA 1.5M Gates 38400 Cells 672-BGA | Altera

EP2A40F672C9 ⚠ 最後購買機會

規格比較

參數 EP2A40F672C9 EP2A40F672C6N
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 最後購買 Obsolete
Family APEX II APEX II
Device Family APEX II PLD —
Logic Elements / Cells 38,400 —
System Gates 1.5 M —
Macros 2,560 —
User I/Os 492 —
腳位數 672 —
封裝 672-BBGA, FC-FBGA (FineLine) 672-ball FineLine BGA
Package Size 27 mm × 27 mm, 1 mm ball pitch —
Core Voltage 1.5 V 1.5 V
Process Technology 0.15 µm all-layer copper, up to 8 metal layers SRAM-based, 0.18 um (per family datasheet)
Logic Family CMOS —
Propagation Delay 1.55 ns —
Internal Speed Grade 366 MHz —
工作溫度 0 °C to 85 °C (commercial) Commercial (0C to +85C)
I/O Standards Supported True-LVDS, LVPECL, PCML, HyperTransport LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL, 1.8V/2.5V/3.3V/5V
安裝類型 Surface Mount Surface Mount
RoHS 狀態 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Logic Elements — 40,000
Maximum System Gates — 1,125,000
Embedded RAM Bits — 442,368
Embedded System Blocks (ESBs) — 160
Maximum User I/O Pins — [DATA_NEEDED: maximum user I/O count]
Speed Grade — C6 (per part number suffix)
Configuration Methods — Passive Serial, Passive Parallel, JTAG
PLL Count — [DATA_NEEDED: PLL count]

資料表與資源

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