EP2S60F484I4N vs EP2S60F484I5N 比較

詳細並排比較 EP2S60F484I4N 由 Intel 與 EP2S60F484I5N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP2S60F484I4N EP2S60F484I5N
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Series Stratix II Stratix II (EP2S60)
Family Stratix II (EP2S60) Field Programmable Gate Array (FPGA)
Logic Elements (LE) 60,440 60,440
Logic Array Blocks (LABs) 3,022 —
Total RAM Bits 2,544,192 —
Number of I/O 334 —
Number of DSP Blocks 18 (typical) —
Number of PLLs 12 (typical) —
封裝 484-BBGA, FCBGA 484-ball FC-FBGA (Flip-Chip Fine-pitch BGA), 1.00 mm pitch
安裝類型 Surface Mount Surface Mount (BGA)
工作溫度 -40C to +100C (Industrial, I4) —
Speed Grade -4 (mid) I5 (industrial, slow-speed for low power)
供應電壓 1.2 V (core) —
RoHS 狀態 Compliant [DATA_NEEDED: rohs status not stated in verified data]
Lead-Free Yes —
Adaptive Logic Modules (ALM) — 24,176
Embedded Memory (bits) — 2,544,192
Embedded Memory (M512/M4K/M-RAM blocks) — M512: 330, M4K: 255, M-RAM: 2
DSP Blocks (18-bit multipliers) — 48 blocks (192 18x18 multipliers)
PLLs — 12 (4 enhanced + 8 fast)
Maximum User I/O Pins — 334
Maximum Fabric Clock — 609.76 MHz
Core Supply Voltage — 1.2 V typical
Process Technology — 90 nm CMOS
工作溫度範圍 — -40 °C to +100 °C (industrial)
Lead-Free / Halogen-Free — [DATA_NEEDED: lead-free / halogen-free status]
Configuration Interface — JTAG (IEEE 1149.1), Passive Serial, Fast Passive Parallel
Design Tool — Quartus II (legacy; current Intel Quartus Prime with Stratix II device support)

資料表與資源

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