EP2S60F672C3 vs EP2S60F672C5 比較
詳細並排比較 EP2S60F672C3 由 Altera 與 EP2S60F672C5 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP2S60F672C3 | EP2S60F672C5 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | Stratix II | Stratix II |
| Logic Elements | 60,440 | 60,440 |
| Adaptive Logic Modules (ALMs) | [DATA_NEEDED: ALM count] | — |
| Total RAM Bits | 2,544,192 | 2,544,192 bits |
| Embedded Multiplier Blocks | [DATA_NEEDED: 9x9 multiplier count] | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | 12 (dedicated 18 × 18 multipliers) |
| User I/Os | 492 | — |
| PLLs | 4 | — |
| Global Clocks | [DATA_NEEDED: global clock count] | — |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Core Voltage | 1.2 V | 1.2 V |
| Speed Grade | C3 | — |
| 封裝 | 672-BBGA, FC-FBGA, 35 x 35 mm, 1.0 mm pitch | 672-ball FC-FBGA (35 × 35 mm, 1 mm pitch) |
| 安裝類型 | Surface Mount | Surface Mount |
| Configuration Modes | PS, PPS, PPA, FPP, JTAG | — |
| 工作溫度 | 0C to +85C (commercial) | — |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Non-RoHS (legacy product, pre-RoHS production runs) |
| Device Family | — | Stratix II FPGA |
| Configurable Logic Blocks (CLBs) | — | 24,176 |
| Maximum User I/Os | — | 492 |
| Operating Frequency | — | Up to 609.76 MHz |
| Operating Temperature Grade | — | Commercial (C5 suffix) |
| 工作溫度範圍 | — | 0°C to +85°C |
| Number of PLLs | — | 4 |
| I/O Standards | — | LVDS, LVTTL, SSTL, HSTL, PCI-X |
| Configuration Scheme | — | Fast Passive Parallel, JTAG, Active Serial |