EP2SGX60EF1152I4N vs EP2SGX60EF1152I3 比較

詳細並排比較 EP2SGX60EF1152I4N 由 Intel 與 EP2SGX60EF1152I3 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Intel
EP2SGX60EF1152I4N EP2SGX60EF1152I4N - 60,440-LCell FPGA, 717 MHz | Intel

EP2SGX60EF1152I4N - 60,440-LCell FPGA, 717 MHz | Intel

EP2SGX60EF1152I4N ✓ 啟用中

規格比較

參數 EP2SGX60EF1152I4N EP2SGX60EF1152I3
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 Obsolete
Device Type FPGA —
Product Family Stratix II GX —
Logic Cells 60,440 —
Embedded Memory 2,544,192 bits —
I/O Count 534 —
Internal Frequency 717 MHz —
供應電壓 1.2 V —
封裝 1,152-ball FBGA 1152-ball FBGA, 35 mm x 35 mm, 1 mm pitch
Package Type Other, 23 x 23 mm, 1 mm pitch, MS-034AAJ-1, FBGA-484 —
Pins 484 —
Device Technology 90 nm —
Logic Blocks 3,022 LABs —
安裝類型 Surface mount Surface Mount (BGA)
Operating Temperature Grade Industrial —
Compliance [DATA_NEEDED: compliance certification details] —
Transceiver Count [DATA_NEEDED: high-speed transceiver count] —
Configuration Memory [DATA_NEEDED: configuration memory specification] —
Package Pinout [DATA_NEEDED: complete ball-map pinout] —
Family — Stratix II GX
Series — EP2SGX60
Logic Elements (LEs) — 60,440
Adaptive Logic Modules (ALMs) — 30,220 (estimated from LEs)
Equivalent Logic Cells (CLBs) — 60,440
Embedded Memory (Bits) — 2,544,192 bits (per DigiKey listing for the I4N variant)
Maximum Internal Frequency — 717 MHz
Combinational Delay (per CLB) — 2.99 ns
Multi-Gigabit Transceivers — [DATA_NEEDED: exact count for EP2SGX60]
Maximum Transceiver Data Rate — 6.375 Gbps (per Stratix II GX family spec)
Total RAM Bits — 2,544,192 bits
Pin/Ball Count — 1152
工作溫度 — -40C to +100C (Industrial, I3 speed grade)
Speed Grade — I3 (Industrial)
Configuration Mode — Enhanced (EPC) - fast parallel via external memory
Process Technology — 90 nm CMOS
RoHS 狀態 — [DATA_NEEDED: not in retrieved snippets]

資料表與資源

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