EP3C55F484I8N vs EP3C55F484C8N 比較
詳細並排比較 EP3C55F484I8N 由 Intel 與 EP3C55F484C8N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP3C55F484I8N | EP3C55F484C8N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Series | Cyclone III | — |
| Logic Elements (LE) | 55,856 | 55,856 |
| Logic Array Blocks (LAB) | 3,491 | — |
| Embedded Memory Bits | 2,396,160 bits (approximately 234 Kbytes) | 2,396,160 |
| Embedded Multipliers (18x18) | 312 | 260 |
| PLLs | 4 | 4 |
| User I/O Pins | 327 | 327 |
| I/O Banks | 8 | — |
| Core Voltage (VCCINT) | 1.2 V nominal (1.15 V to 1.25 V) | 1.2 V |
| Auxiliary Voltage (VCCAUX) | 2.5 V nominal | — |
| I/O Voltage (VCCIO) | 1.2 V to 3.3 V per bank | — |
| 封裝 | 484-ball FBGA (FineLine BGA), 23 mm x 23 mm | 484-BGA (FBGA), 23 x 23 mm, 1.0 mm pitch |
| 安裝類型 | Surface Mount | Surface Mount (BGA) |
| 工作接面溫度 | -40 C to +100 C (industrial, suffix I8) | — |
| Speed Grade | 8 (slowest Cyclone III timing bin) | — |
| Process Technology | 65 nm low-power CMOS | — |
| Configuration Modes | AS, PS, FPP, JTAG | — |
| RoHS 狀態 | Compliant | — |
| Lead-Free | Yes | — |
| MSL 等級 | 3 | — |
| Device Family | — | Cyclone III |
| Memory Blocks (M9K) | — | 260 |
| Maximum Internal Frequency | — | 472 MHz |
| Package Height | — | 2.60 mm |
| Operating Temperature (Commercial) | — | 0 C to +85 C |
| Process Node | — | 65 nm TSMC low-power |
| Configuration | — | SRAM-based, JTAG / AS / PS modes |
| Lead-Free / RoHS | — | Yes - lead-free, RoHS compliant |