EP3SL200H780C4LN vs EP3SL200H780C3N 比較
詳細並排比較 EP3SL200H780C4LN 由 Altera 與 EP3SL200H780C3N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP3SL200H780C4LN | EP3SL200H780C3N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | NRND |
| Series | Stratix III L | — |
| Logic Elements | 200,000 | 200,000 |
| Logic Array Blocks (LABs) | 8,000 | 8,000 |
| User I/Os | 488 | 488 |
| Total Memory Bits | 10,901,504 | — |
| 腳位數 | 780 | — |
| 封裝 | 780-BBGA / HBGA / FCBGA | 780-Ball FCBGA (HBGA), 29 x 29 mm |
| 安裝類型 | Surface Mount | Surface Mount |
| Core Supply Voltage | 0.86 V to 1.15 V | — |
| 工作溫度 | 0 C to +70 C (commercial, 'C' grade) | 0C to +85C (commercial) |
| Speed Grade | 4 (commercial, slowest of grade 4) | C3 (commercial, -3 speed) |
| Transceivers | Multi-quad, up to 6.375 Gbps | 24 channels, up to 3.75 Gbps |
| DSP Blocks (18x18 multipliers) | [DATA_NEEDED: exact multiplier count] | — |
| PLLs | 8 | 12 (Stratix III PLL array) |
| Configuration | JTAG / Passive Serial / Fast Passive Parallel | JTAG IEEE Std 1149.1, passive/active serial |
| RoHS 狀態 | Compliant | — |
| Lead-Free | Yes | — |
| Family | — | Stratix III L (low-power) |
| Process Node | — | 40 nm |
| Embedded Memory Bits | — | 10,901,504 bits |
| Maximum Internal Clock Frequency | — | 800 MHz |
| DSP Blocks | — | 384 |
| Voltage - Core | — | 0.9 V / 1.0 V (core, VCC) |
| Voltage - I/O | — | 1.2 V to 3.3 V (VCCIO banks) |
| MSL 等級 | — | 3 |
| Lead-Free / RoHS | — | Yes |
| Mounting Pitch | — | 1.0 mm ball pitch |